
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 6
SMSC SIO10N268
DATASHEET
8.10.7.9
8.10.7.10
8.10.7.11
8.10.7.12
8.10.7.13
8.10.7.14
8.10.8
8.10.8.1
8.11
8.12
8.13
8.13.1
8.13.1.1
8.13.1.2
8.13.1.3
8.13.1.4
8.13.1.5
8.13.1.6
8.13.2
8.13.2.1
8.13.3
8.13.3.1
8.14
8.14.1
8.14.1.1
8.14.1.2
8.14.1.3
8.14.1.4
8.14.1.5
8.14.1.6
8.14.1.7
8.14.2
8.15
8.15.1
8.15.2
8.15.3
8.15.4
8.16
8.16.1
8.16.2
8.16.3
8.16.4
8.16.5
8.17
8.17.1
8.18
8.18.1
Chapter 9
9.1
Runtime Registers Block Summary ................................................................................................153
9.2
Runtime Registers Block Description..............................................................................................154
Chapter 10
Configuration................................................................................................................163
10.1
Configuration Access Ports..........................................................................................................163
10.2
Configuration State ......................................................................................................................163
10.2.1
Entering the Configuration State.......................................................................................................163
10.2.2
Configuration Register Programming................................................................................................163
10.2.3
Exiting the Configuration State..........................................................................................................164
10.2.3.1
Programming Example..................................................................................................................164
FIFO Operation..............................................................................................................................130
DMA Transfers ............................................................................................................................131
DMA Mode - Transfers from the FIFO to the Host.......................................................................131
Programmed I/O Mode or Non-DMA Mode..................................................................................131
Programmed I/O - Transfers from the FIFO to the Host ..............................................................131
Programmed I/O - Transfers from the Host to the FIFO ..............................................................132
Parallel Port Floppy Disk Controller...................................................................................................132
FDC on Parallel Port Pin................................................................................................................133
Watchdog Timer...........................................................................................................................134
LED Functionality.........................................................................................................................135
Power Management.....................................................................................................................135
FDC Power Management..................................................................................................................135
DSR From Powerdown..................................................................................................................136
Wake Up From Auto Powerdown ..................................................................................................136
Register Behavior..........................................................................................................................136
Pin Behavior..................................................................................................................................136
System Interface Pins....................................................................................................................137
FDD Interface Pins........................................................................................................................137
UART Power Management ...............................................................................................................138
Exit Auto Powerdown ....................................................................................................................138
Parallel Port.......................................................................................................................................138
Exit Auto Powerdown ....................................................................................................................138
Serial IRQ.....................................................................................................................................138
Timing Diagrams For SER_IRQ Cycle..............................................................................................139
SER_IRQ Cycle Control ................................................................................................................139
SER_IRQ Data Frame...................................................................................................................140
Stop Cycle Control.........................................................................................................................141
Latency..........................................................................................................................................141
EOI/ISR Read Latency ..................................................................................................................141
AC/DC Specification Issue.............................................................................................................142
Reset and Initialization...................................................................................................................142
Routable IRQ Inputs..........................................................................................................................142
PCI CLKRUN Support..................................................................................................................143
Overview...........................................................................................................................................143
CLKRUN# for Serial IRQ...................................................................................................................143
CLKRUN# for LDRQ# .......................................................................................................................143
Using CLKRUN#...............................................................................................................................143
General Purpose I/O....................................................................................................................145
GPIO Pins.........................................................................................................................................145
Description........................................................................................................................................146
GPIO Control.....................................................................................................................................148
GPIO Operation ................................................................................................................................148
GPIO, PME and SMI Functionality....................................................................................................150
System Management Interrupt (SMI)...........................................................................................151
SMI Registers....................................................................................................................................151
PME Support................................................................................................................................151
PME Registers..................................................................................................................................152
Runtime Registers............................................................................................................153