
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
Rev. 0.5 (03-24-05)
Page 36
SMSC SIO10N268
DATASHEET
Note 8.5
LPC Memory transactions are only enabled if the MEM_EN bit is set to ‘1’ and the FWH_SEL bit is set to
‘0’ in the FWH ID Select register.
8.3.3
LFRAME# Usage
LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort
or time-out condition. This signal is to be used by the SIO10N268 to know when to monitor the bus for a
cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start
or stop of a cycle, and that the SIO10N268 monitors the bus to determine whether the cycle is intended for
it. The use of LFRAME# allows the SIO10N268 to enter a lower power state internally. There is no need
for the SIO10N268 to monitor the bus when it is inactive, so it can decouple its state machines from the
bus, and internally gate its clocks.
When the SIO10N268 samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on
the next clock and monitor the bus for new cycle information.
The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification Revision
1.0.
8.3.4
Field Definitions
LPC transactions are defined as being comprised of multiple fields. These fields may be one or more
nibbles in length (nibble=4 bits). All LPC transactions begin with a START field and a Cycle Type/Direction
field. The START field is used to initiate/terminate LPC transactions. The Cycle Type/Direction field is
used to define the cycle type (memory, I/O, DMA) and direction (read/write) for LPC cycles. The remaining
fields of data being transfered are based on specific fields that are used in various combinations,
depending on the cycle type. These remaining fields are driven on to the LAD[3:0] signal lines to
communicate address, control and data information over the LPC bus between the host and the
SIO10N268. See the
Low Pin Count (LPC) Interface Specification
Revision 1.0 from Intel, Section 4.2 for
definition of these fields. The following sections describe the supported cycle types.
NOTE:
I/O, DMA, and Memory cycles use a START field of 0000.
8.3.4.1
I/O Read and Write Cycles
The SIO10N268 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO
accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes
is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will
break it up into 8-bit transfers.
See the
Low Pin Count (LPC) Interface Specification
Reference, Section 5.2, for the sequence of cycles
for the I/O Read and Write cycles.
8.3.4.2
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the SIO10N268. DMA write
cycles involve the transfer of data from the SIO10N268 to the host (main memory). Data will be coming
from or going to a FIFO and will have minimal Sync times. Data transfers to/from the SIO10N268 are 1
byte.