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參數資料
| 型號： | SiI1161CTU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機 |
| 文件頁數： | 9/46頁 |
| 文件大?。?/td> | 398K |
| 代理商： | SII1161CTU |
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SiI
1161
PanelLink Receiver
Data Sheet
5
SiI
-DS-0096-D
General AC Specifications
Table 2. General AC Specifications
Parameter
Intra-Pair (+ to -) Differential Input Skew
Channel to Channel Differential Input Skew
Worst Case Differential Input Clock Jitter
tolerance
ODCK Cycle Time (one pixel per clock)
ODCK Frequency (one pixel per clock)
ODCK Cycle Time (two pixels per clock)
ODCK Frequency (two pixels per clock)
Output Clock Duty Cycle
Delay PD# / PDO# Low to high-Z outputs
Link disabled (DE inactive) to SCDT low
Link enabled (DE active) to SCDT high
Delay from RXC+ Inactive to high-Z outputs
Delay from RXC+ active to data active
ODCK high to even data output
SDA Data Valid Delay from SCL high to low
transition
Control Pulse Width
PD# Signal Low Time required for a valid I
2
C
reset
Symbol
T
DPS
T
CCS
T
IJIT
R
CIP
F
CIP
R
CIP
F
CIP
T
DUTY
T
PDL
T
HSC
T
FSC
T
CLKPD
T
CLKPU
T
ST
T
I2CDVD
Conditions
165MHz
165MHz
65 MHz
112 MHz
165 MHz
one pixel per
clock
Min
6
25
12
12.5
40%
4
Typ
0.25
Max
245
4
465
270
182
40
165
80
82.5
60%
10
50
10
10
100
700
Units
ps
ns
ps
ps
ps
ns
MHz
ns
MHz
ns
ms
DE edges
μ
s
μ
s
R
CIP
ns
Notes
1
1
2,3
1
1
1
1
7
1
1
1
1
5
two pixels per
clock
C
L
= 400pf
T
CTLW
T
RESET
2
10
R
CIP
μ
s
6
1
Notes
1. Guaranteed by design.
2. Jitter defined per DVI 1.0 Specification, Section 4.6 – Jitter Specification.
3. Jitter measured with Clock Recovery Unit per DVI 1.0 Specification, Section 4.7 – Electrical Measurement
Procedures.
4. Measured with transmitter powered down.
5. All Standard Mode I
2
C (100kHz and 400kHz) timing requirements are guaranteed by design.
6. Control pulses include HSYNC, VSYNC, CTL1, CTL2 and CTL3. Pulses narrower than this minimum width
specification are filtered out in the receiver and will not be seen at the output pins.
7. ODCK duty cycle is independent of the differential input clock duty cycle and the transmitter IDCK duty cycle.
DC and AC parameters specific to the operating mode of the
SiI
1161
are listed on the following pages.
The output pin timing specifications are dependent on the selection of output drive capability. Specifications are
listed for two modes:
SiI
161B mode, which requires no I
2
C initialization; and
SiI
1161
mode, which allows for
optimization of input data recovery and output drive using I
2
C programming. Designers should choose the mode
most suited to their board-level requirements.
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