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參數(shù)資料
| 型號： | SiI1161CTU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機 |
| 文件頁數(shù)： | 41/46頁 |
| 文件大?。?/td> | 398K |
| 代理商： | SII1161CTU |
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SiI
1161
PanelLink Receiver
Data Sheet
37
SiI
-DS-0096-D
Receiver Layout
The receiver chip should be placed as close as possible to the input connector that carries the TMDS signals.
For a system using the industry-standard DVI connector (see
http://www.ddwg.org
), the differential lines should
be routed as directly as possible from connector to receiver. Differential pair length is not critical but ideally
should be less than 10cm.
PanelLink devices are tolerant of skews between differential pairs, so spiral skew compensation for path length
differences is not required. However, each conductor of the differential pair should be routed together with equal
trace lengths. Vias should be avoided, but if used they should be placed on both signal lines of the differential
pair in a way that gives both lines equivalent reflection characteristics. Figure 28 illustrates acceptable routing
practices for TMDS signals from a DVI connector, while Figure 29 shows an example of actual trace routing.
Figure 28. General Signal Routing Recommendations
RX C-
RX C+
RX 0-
RX 0+
RX 1-
RX 1+
RX 2-
RX 2+
1
9
1
Figure 29. Signal Trace Routing Example
<10cm
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