- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365565 > SiI1161CTU (Silicon Image, Inc.) PanelLink Receiver PDF資料下載
參數(shù)資料
| 型號： | SiI1161CTU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | PanelLink Receiver |
| 中文描述： | PanelLink接收機(jī) |
| 文件頁數(shù)： | 36/46頁 |
| 文件大?。?/td> | 398K |
| 代理商： | SII1161CTU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
SiI
1161
PanelLink Receiver
Data Sheet
SiI
-DS-0096-D
32
Recommendation: Putting a 1000pF capacitor and a 10k
resistor on the PD# pin is sufficient to provide the
needed reset delay. If the PD# is already controlled by external logic, that logic should be used to perform the
reset function instead.
Vcc
10k
1000pF
PD#
Si
I
1161
Figure 22. Recommended RESET Circuit
For existing circuit designs where these methods are impractical to implement, other solutions may be possible. Contact your
Silicon Image technical representative for information.
Using
SiI
1161 in Multiple-Input Applications
Two
SiI
1161 parts can be connected with their outputs in parallel to permit video from either of two independent
DVI inputs to be recovered and sent to a single image processing device (such as a scaler). As an example of
another application, one
SiI
1161 part can be used with its outputs in parallel with an ADC to support a dual mode
monitor.
These applications may require the following considerations.
Use the PDO# pin to disable the outputs from the
SiI
1161 when it is not in use. The outputs will be tri-
stated so that other devices can drive the lines. The chip engages internal pull-down resistors to prevent
the outputs from floating, but these are very weak and will not adversely affect other devices driving the
bus.
Use the MODE pin to enable or disable the I
2
C interface from responding. All
SiI
1161 parts in the system
will use the same I
C address, so only one can be enabled for I
C access at a time.
The PD# pin can be used in place of both PDO# and MODE. Its assertion will: disable the outputs from the
SiI
1161; power down the internal
SiI
1161 logic; and disable I
2
C access.
Note:
Asserting the PD# pin or toggling the MODE pin will reset the state of the registers to their default settings,
so upon deassertion all special register settings will need to be rewritten.
Using
SiI
1161 to Replace T
I
TFP401
The
SiI
1161 device pinout is very similar to that of the T
I
TFP401 receiver. Applications can immediately benefit
from improved performance over the T
I
part, even if the programmability feature of the
SiI
1161 device is not
used. However, there are some areas that require attention when replacing the T
I
TFP401 part.
When the staggered output mode is used, the T
I
TFP401 part times its DE signal to coincide with the first
(ODD) data pixel. The
SiI
1161 device times its DE signal to coincide with the first (EVEN) data pixel, one
quarter clock period later. The
SiI
1161 staggered output timing is provided on page.17.
If the system has been designed to match the T
I
TFP401 timing noted above, it is often possible to adapt
the
SiI
1161 by using the OCK_INV, ST, and CKST selections to meet system timing requirements. This
is possible because the
SiI
1161 part has better timing characteristics in most applications.
Contact your Silicon Image representative for additional application-specific suggestions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII1162 | PanelLink Transmitter |
| SII1169 | PanelLink Receiver |
| SII1171 | PanelLink Receiver |
| SII1172 | PanelLink Transmitter |
| SiI1362 | PanelLink Transmitters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII1162 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
| SII1162CSU | 制造商:Silicon Image Inc 功能描述: |
| SII1169 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1171 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Receiver |
| SII1172 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PanelLink Transmitter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。