參數(shù)資料
型號: SI9750
廠商: Vishay Intertechnology,Inc.
英文描述: In-Rush Current Limit MOSFET Driver
中文描述: 在浪涌電流限制MOSFET驅(qū)動器
文件頁數(shù): 6/9頁
文件大小: 184K
代理商: SI9750
Si9750
Vishay Siliconix
S-60752—Rev. C, 05-Apr-99
6
FaxBack 408-970-5600, request 70028
www.siliconix.com
di/dt Limiting On Hot and Cold Insertion (GATE pin)
The GATE pin provides a constant current source that is used
to control the rate of rise of the gate of the MOSFET, and
hence to control the di/dt of the load and source current. The
equation that governs the gate current is:
Typically, a 33-nF capacitor should be connected from the
GATE pin to ground. If a large I
SOURCE
is needed for high di/
dt, a 330-
resistor in series with C
GATE
may be necessary to
prevent oscillation. In the case that V
DD
> 6 V, a resistor of
approximately 330
is also recommended in series with the
gate (Figure 1).
Reference Bias Current
(R
BIAS
pin)
This pin sets the internal current used by R
LIMSET
to
determine all the current limit points. Typically R
BIAS
=
12.5 k
which sets a 20-
μ
A bias current. The equation which
relates R
BIAS
to I
BIAS
is:
Power on Reset (POR)
(V
DD
pin)
This function monitors the voltage on the V
DD
pin and signals
the system if all input voltage requirements have been met. At
turn-on when V
DD
> 2.7 V " 200 mV, a POR signal is
generated for a duration of 100
μ
s. After this point the system
is released into operation. If V
DD
falls below 2.7 V " 200 mV, a
second POR signal will be generated. If two POR signals are
detected, this indicates that the source for V
DD
is not capable
of supplying the load current. The IC then turns off the
MOSFET and initiates its retry period, hence fully protecting
the MOSFET from an over-power condition.
Boost Converter
(COIL, BOOST pins)
The boost converter generates the gate drive for the external
n-channel MOSFET. This is limited to typically V
DD
+ 11 V.
The boost inductor should typically be 100
μ
H, <3.5
,
>180 mA dc, and the boost capacitor should be 100 nF.
Logic Control
(STATUS, ENABLE, RESET, V
RST
and C
RST
pins)
STATUS.
The status monitor detects when the load voltage is
90% of input voltage, V
LOAD
> 0.9 x V
DD
. This pin is an open-
drain NMOS output, capable of sinking 200
μ
A at V
OL
= 0.4 V.
If this pin is used in conjunction with the ENABLE of another
unit, power supply sequencing (or daisy-chaining) is easily
implemented.
ENABLE.
This CMOS logic compatible input serves as the
on/off control pin. This pin has 40-
μ
A minimum pull-up to
V
DD
.
RESET (V
RST
, C
RST
, RESET pins).
This is a standard
implementation of the microprocessor reset function. A
comparator looks at the voltage on V
RST
pin and compares it
with 1.25 V. This function is programmable by using an
external voltage divider. When V
RST
is higher than 1.25 V, the
reset signal is delayed by the C
RST
pin, defined by Equation
(6) and then goes high (Figure 8)
.
FIGURE 2.
Typical Operation Under Start-up Condition with
an Overcurrent Fault Applied to the Output
I
SOURCE
1.25V
BIAS
)
---------------
×
12mA
for R
BIAS
12.5k
=
(
=
=
(4)
I
BIAS
BIAS
12.5k
=
------------------------
20
μ
A
for R
BIAS
(
)
=
=
(5)
Reset delay t
RSTD
10
4
C
RST
×
(6)
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