Si5366
10
Rev. 1.0
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =2.97
CLOAD =5 pF
——
2
ns
Output Duty Cycle
Uncertainty @
622.08 MHz
CKODC
100
Load
Line-to-Line
Measured at 50% Point
(Not for CMOS)
——
±40
ps
LVCMOS Input Pins
Minimum Reset Pulse
Width
tRSTMN
1—
—
s
Input Capacitance
Cin
——
3
pF
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD =20pF
—25
—
ns
LOSn Trigger Window
LOSTRIG
From last CKINn
to
Internal detection of LOSn
—
4.5 x N3
TCKIN
Time to Clear LOL
after LOS Cleared
tCLRLOL
LOS to LOL
Fold = Fnew
Stable XA/XB reference
—10
—
ms
Device Skew
Output Clock Skew
tSKEW
of CKOUTn to of
CKOUT_m, CKOUTn
and CKOUT_m at same
frequency
——
100
ps
Phase Change due to
Temperature
Variation*
tTEMP
Max phase changes from
–40 to +85 °C
—300
500
ps
Table 3. AC Characteristics
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
*Note: Input to output phase skew after an ICAL is not controlled and can assume any value.