參數(shù)資料
型號(hào)： SI5366-C-GQR
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK MULTIPLIER PREC 100TQFP
標(biāo)準(zhǔn)包裝： 250
系列： DSPLL®
類(lèi)型： 時(shí)鐘放大器，振動(dòng)衰減器
PLL： 是
輸入： 時(shí)鐘
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 4:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.05GHz
除法器/乘法器： 無(wú)/是
電源電壓： 1.71 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
Si5366
20
Rev. 1.0
21
FS_ALIGN
I
LVCMOS
FSYNC Alignment Control.
If CK_CONF = 1, a logic high on this pin causes the FS_OUT
phase to be realigned to the rising edge of the currently active
input sync (CKIN3 or CKIN4).
0 = No realignment.
1 = Realignment.
This pin has a weak pull-down.
22
AUTOSEL
I
3-Level
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tri-
state.
29
30
CKIN4+
CKIN4–
IMULTI
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input asso-
ciated with the CKIN2 clock when CK_CONF = 1.
32
42
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three-level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have
both a weak pull-up and a weak pull-down and default to M.
Some designs may require an external resistor voltage divider
when driven by an active device.
34
35
CKIN2+
CKIN2–
IMULTI
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
37
DBL2_BY
I
3-Level
CKOUT2 Disable/PLL Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and PLL
bypass mode.
L = CKOUT2 Enabled.
M = CKOUT2 Disabled.
H = BYPASS Mode with CKOUT2 enabled.
Bypass mode does not support CMOS outputs.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tri-
state.
39
40
CKIN3+
CKIN3–
IMULTI
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input asso-
ciated with the CKIN1 clock when CK_CONF = 1.
44
45
CKIN1+
CKIN1–
IMULTI
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
Table 8. Si5366 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5366-EVB 制造商:Silicon Laboratories Inc 功能描述:
SI5367 制造商:SILABS 制造商全稱:SILABS 功能描述:レP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Si5367/68-EVB 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 Si5367/Si5368 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
Si5367A-B-GQ 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 uP-PROGRAMMABE CLK MULT 10 MHZ-1.4 GHZ RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SI5367A-B-GQR 制造商:Silicon Laboratories Inc 功能描述:
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