(VDD = 1.8 V –5% to +10%, 2.5 V" />
參數(shù)資料
型號： SI5338K-A-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 5/44頁
文件大?。?/td> 0K
描述： IC CLK GEN I2C BUS PROG 24QFN
標準包裝： 490
系列： MultiSynth™
類型： *
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 700MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤
Si5338
Rev. 1.3
13
Table 12. Jitter Specifications1,2,3
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
GbE Random Jitter
(12kHz–20MHz)4
JGbE
CLKIN = 25 MHz
All CLKn at 125 MHz5
—
0.7
1
ps RMS
GbE Random Jitter
(1.875–20 MHz)
RJGbE
CLKIN = 25 MHz
All CLKn at 125 MHz5
—
0.38
0.79
ps RMS
OC-12 Random Jitter
(12 kHz–5 MHz)
JOC12
CLKIN = 19.44 MHz
All CLKn at
155.52 MHz5
—
0.7
1
ps RMS
PCI Express 1.1 Common
Clocked
Total Jitter6
—
20.1
33.6
ps pk-pk
PCI Express 2.1 Common
Clocked
RMS Jitter6, 10 kHz to
1.5 MHz
—
0.15
1.47
ps RMS
RMS Jitter6, 1.5 MHz to
50 MHz
—
0.58
0.75
ps RMS
PCI Express 3.0 Common
Clocked
RMS Jitter6
—
0.15
0.45
ps RMS
Period Jitter
JPER
N = 10,000 cycles7
—
10
30
ps pk-pk
Cycle-Cycle Jitter
JCC
N = 10,000 cycles
Output MultiSynth
operated in integer or
fractional mode7
—
9
29
ps pk8
Random Jitter
(12kHz–20MHz)
RJ
Output and feedback
MultiSynth in integer or
fractional mode7
—
0.7
1.5
ps RMS
Notes:
1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and
are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation.
2. For best jitter performance, keep the single ended clock input slew rates at Pins 3 and 4 more than 1.0 V/ns and the
differential clock input slew rates more than 0.3 V/ns.
3. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there
is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration
implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact Silicon Labs
for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS
outputs have little to no effect upon jitter.
4. DJ for PCI and GbE is < 5 ps pp
5. Output MultiSynth in Integer mode.
6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter.
See AN562 for details. Jitter is measured with the Intel Clock Jitter Tool, Ver. 1.6.4.
7. Input frequency to the Phase Detector between 25 and 40 MHz and any output frequency > 5MHz.
8. Measured in accordance with JEDEC standard 65.
9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges.
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