參數(shù)資料
型號(hào)： SI5338K-A-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 29/44頁
文件大?。?/td> 0K
描述： IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝： 490
系列： MultiSynth™
類型： *
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 700MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤
Si5338
Rev. 1.3
35
15
VDDO2
VDD
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK2A,B.
A 0.1 F capacitor must be located very close to this pin. If CLK2 is
not used, this pin must be tied to VDD (pin 7, 24).
16
VDDO1
VDD
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK1A,B.
A 0.1 F capacitor must be located very close to this pin. If CLK1 is
not used, this pin must be tied to VDD (pin 7, 24).
17
CLK1B
O
Multi
Output Clock B for Channel 1.
May be a single-ended output or half of a differential output with
CLK1A being the other differential half. If unused, leave this pin
floating.
18
CLK1A
O
Multi
Output Clock A for Channel 1.
May be a single-ended output or half of a differential output with
CLK1B being the other differential half. If unused, leave this pin
floating.
19
SDA
I/O
LVCMOS
I2C Serial Data.
This is the serial data for the I2C bus. A pullup resistor at this pin is
required. Typical values would be 1–4 k
. See the I2C bus spec
for more information. This pin is 3.3 V tolerant regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, 24. See Register
27.
20
VDDO0
VDD
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK0A,B.
A 0.1 F capacitor must be located very close to this pin. If CLK0 is
not used, this pin must be tied to VDD (pin 7, 24).
21
CLK0B
O
Multi
Output Clock B for Channel 0.
May be a single-ended output or half of a differential output with
CLK0A being the other differential half. If unused, leave this pin
floating.
22
CLK0A
O
Multi
Output Clock A for Channel 0.
May be a single-ended output or half of a differential output with
CLK0B being the other differential half. If unused, leave this pin
floating.
23
RSVD_GND
GND
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
24
VDD
Supply
Core Supply Voltage.
The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 F
bypass capacitor should be located very close to this pin.
GND
PAD
GND
Ground Pad.
This is the large pad in the center of the package. Device
specifications cannot be guaranteed unless the ground pad is
properly connected to a ground plane on the PCB. See Table 19,
“PCB Land Pattern,” on page 39 for ground via requirements.
Table 16. Si5338 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5338K-A-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-Program Clk Gen 0.16-710MHz Pin-Ctrl RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5338K-B01064-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338K-B01077-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338K-B01077-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
SI5338K-B01116-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
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