參數(shù)資料
型號: SI5338K-A-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 30/44頁
文件大?。?/td> 0K
描述: IC CLK GEN I2C BUS PROG 24QFN
標準包裝: 490
系列: MultiSynth™
類型: *
PLL:
輸入: CML,HCSL,HSCL,LVDS,LVPECL,晶體
輸出: CMOS,HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應商設備封裝: 24-QFN(4x4)
包裝: 托盤
Si5338
36
Rev. 1.3
8. Device Pinout by Part Number
The Si5338 is orderable in three different speed grades: Si5338A/D/G/K/N have a maximum output clock
frequency limit of 710 MHz. Si5338B/E/H/L/P have a maximum output clock frequency of 350 MHz. Si5338C/F/J/
M/Q have a maximum output clock frequency of 200 MHz.
Devices are also orderable according to the pin control functions available on Pins 3 and 4:
CLKIN—single-ended clock input
I2C_LSB—determines the LSB bit of the 7-bit I2C address
FINC—frequency increment pin
FDEC—frequency decrement pin
PINC—phase increment pin
PDEC—phase decrement pin
FDBK—single-ended feedback input
OEB—output enable
Table 17. Pin Function by Part Number
Pin #
Si5338A: 710 MHz
Si5338B: 350 MHz
Si5338C: 200 MHz
Si5338D: 710 MHz
Si5338E: 350 MHz
Si5338F: 200 MHz
Si5338G: 710 MHz
Si5338H: 350 MHz
Si5338J: 200 MHz
Si5338K: 710 MHz
Si5338L: 350 MHz
Si5338M: 200 MHz
Si5338N: 710 MHz
Si5338P: 350 MHz
Si5338Q: 200 MHz
1CLKIN1
CLKIN1
CLKIN1
CLKIN1
2CLKINB1
CLKINB1
CLKINB1
CLKINB1
3CLKIN2
PINC
FINC
OEB
CLKIN2
4
I2C_LSB
PDEC
FDEC
I2C_LSB
5FDBK4
FDBK4
FDBK4
FDBK4
6FDBKB4
FDBKB4
FDBKB4
7
VDD
8
INTRINTRINTRINTRINTR
9
CLK3B
10
CLK3A
11
VDDO3
12
SCL
13
CLK2B
14
CLK2A
15
VDDO2
16
VDDO1
Notes:
1. CLKIN/CLKINB on pins 1 and 2 are differential clock inputs or XTAL inputs.
2. CLKIN on pin 3 is a single-ended clock input.
3. FDBK on pin 4 is a single-ended feedback input.
4. FDBK/FDBKB on pins 5 and 6 are differential feedback inputs.
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