(VDD = 1.8 V –5% to +10%, 2.5 V " />
參數(shù)資料
型號(hào): SI5338K-A-GM
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 41/44頁(yè)
文件大?。?/td> 0K
描述: IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝: 490
系列: MultiSynth™
類型: *
PLL:
輸入: CML,HCSL,HSCL,LVDS,LVPECL,晶體
輸出: CMOS,HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 托盤
Si5338
6
Rev. 1.3
Table 5. Performance Characteristics
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
PLL Acquisition Time
tACQ
——
25
ms
PLL Tracking Range
fTRACK
5000
20000
ppm
PLL Loop Bandwidth
fBW
—1.6
MHz
MultiSynth Frequency
Synthesis Resolution
fRES
Output frequency < Fvco/8
0
1
ppb
CLKIN Loss of Signal Detect
Time
tLOS
—2.6
5
s
CLKIN Loss of Signal Release
Time
tLOSRLS
0.01
0.2
1
s
PLL Loss of Lock Detect Time
tLOL
—5
10
ms
POR to Output Clock Valid
(Pre-programmed Devices)
tRDY
——
2
ms
Input-to-Output Propagation
Delay
tPROP
Buffer Mode
(PLL Bypass)
—2.5
4
ns
Output-Output Skew
tDSKEW
Rn divider = 11
——
100
ps
POR to I2C Ready
——
15
ms
Programmable Initial
Phase Offset
POFFSET
–45
+45
ns
Phase Increment/Decrement
Accuracy
PSTEP
——
20
ps
Phase Increment/Decrement
Range
PRANGE
–45
+45
ns
MultiSynth range for phase
increment/decrement
fPRANGE
5—
Fvco/82
MHz
Phase Increment/Decrement
Update Time
PUPDATE
Pin control2,3
MultiSynth output >18 MHz
667
ns
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
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