參數(shù)資料
型號： SI5338A-A-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： IC CLK GEN QUAD 700MHZ 24-QFN
標(biāo)準(zhǔn)包裝： 490
系列： MultiSynth™
類型： 時鐘發(fā)生器
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 700MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤
產(chǎn)品目錄頁面： 628 (CN2011-ZH PDF)
配用： 336-1747-ND - KIT PROG FIELD SI5338/4/0
336-1556-ND - BOARD EVALUATION SI5338
其它名稱： 336-1553-5
Si5338
34
Rev. 1.3
5,6
IN5/IN6
I
Multi
FDBK/FDBKB.
These pins can be used as a differential feedback input in zero
delay mode or as a secondary clock input. See section 3.2,
Figure 3, for termination details. See "3.10.6. Zero-Delay Mode" on
page 27 for zero delay mode set-up. Inputs to these pins must be
ac-coupled.
When not in use, leave IN5 unconnected and IN6 connected to
GND.
7
VDD
Supply
Core Supply Voltage.
This is the core supply voltage, which can operate from a 1.8, 2.5,
or 3.3 V supply. A 0.1 F bypass capacitor should be located very
close to this pin.
8
INTR
O
Open Drain
Interrupt.
A typical pullup resistor of 1–4 k
is used on this pin. This pin can
be pulled up to a supply voltage as high as 3.6 V regardless of the
other supply voltages on pins 7, 11, 15, 16, 20, and 24. The inter-
rupt condition allows the pull up resistor to pull the output up to the
supply voltage.
9
CLK3B
O
Multi
Output Clock B for Channel 3.
May be a single-ended output or half of a differential output with
CLK3A being the other differential half. If unused, leave this pin
floating.
10
CLK3A
O
Multi
Output Clock A for Channel 3.
May be a single-ended output or half of a differential output with
CLK3B being the other differential half. If unused, leave this pin
floating.
11
VDDO3
VDD
Supply
Output Clock Supply Voltage.
Supply voltage (3.3, 2.5, 1.8, or 1.5 V) for CLK3A,B. A 0.1 F
capacitor must be located very close to this pin. If CLK3 is not
used, this pin must be tied to VDD (pin 7, 24).
12
SCL
I
LVCMOS
I2C Serial Clock Input.
This is the serial clock input for the I2C bus. A pullup resistor at this
pin is required. Typical values would be 1–4 k
. See the I2C bus
spec for more information. This pin is 3.3 V tolerant regardless of
the other supply voltages on pins 7, 11, 15, 16, 20, 24. See Regis-
ter 27.
13
CLK2B
O
Multi
Output Clock B for Channel 2.
May be a single-ended output or half of a differential output with
CLK2A being the other differential half. If unused, leave this pin
floating.
14
CLK2A
O
Multi
Output Clock A for Channel 2.
May be a single-ended output or half of a differential output with
CLK2B being the other differential half. If unused, leave this pin
floating.
Table 16. Si5338 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5338A-A-GMR 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-program Clk gen 0.16 - 710 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5338A-B00302-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338A-B00302-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
SI5338A-B00419-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338A-B01206-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
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