CKOVOL for output low " />
參數(shù)資料
型號: SI5324D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 67/72頁
文件大小: 0K
描述: IC CLOCK MULT 2KHZ-150MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 150MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5324
Rev. 1.1
7
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
CKOIO
ICMOS[1:0] = 11
VDD =1.8 V
—7.5
mA
ICMOS[1:0] = 10
VDD =1.8 V
—5.5
mA
ICMOS[1:0] = 01
VDD =1.8 V
—3.5
mA
ICMOS[1:0] = 00
VDD =1.8 V
—1.75
mA
ICMOS[1:0] = 11
VDD =3.3 V
—32
mA
ICMOS[1:0] = 10
VDD =3.3 V
—24
mA
ICMOS[1:0] = 01
VDD =3.3 V
—16
mA
ICMOS[1:0] = 00
VDD =3.3 V
—8
mA
2-Level LVCMOS Input Pins
Input Voltage Low
VIL
VDD =1.71V
0.5
V
VDD =2.25V
0.7
V
VDD =2.97V
0.8
V
Input Voltage High
VIH
VDD =1.89V
1.4
V
VDD =2.25V
1.8
V
VDD =3.63V
2.5
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD ≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
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