參數(shù)資料
型號: SI5324D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 55/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-150MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 150MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5324
Rev. 1.1
59
5.1. ICAL
The device's registers must be configured for the intended applications. After the part is configured, the part must
perform a calibration procedure when there is a stable clock on the selected CLKINn input. The calibration process
is triggered by writing a "1" to bit D6 in register 136. See the Family Reference Manual for details. In addition, after
a successful calibration operation, changing any of the Registers indicated in Table 12 requires that a calibration be
performed again by the same procedure (writing a "1" to bit D6 in register 136).
Table 12. ICAL-Sensitive Registers
Address
Register
0
BYPASS_REG
0
CKOUT_ALWAYS_ON
1
CK_PRIOR1
1
CK_PRIOR2
2
BWSEL_REG
4HIST_DEL
5ICMOS
7FOSREFSEL
9HIST_AVG
10
DSBL1_REG
10
DSBL2_REG
11
PD_CK1
11
PD_CK2
19
FOS_EN
19
FOS_THR
19
LOCKT
19
VALTIME
25
N1HS
31
NC1_LS
34
NC2_LS
40
N2_HS
40
N2_LS
43
N31
46
N32
55
CLKIN1RATE
55
CLKIN2RATE
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