參數(shù)資料
型號: SI5324D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-150MHZ 36VQFN
標準包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 150MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Rev. 1.1 1/14
Copyright 2014 by Silicon Laboratories
Si5324
Features
Applications
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier
for applications requiring sub 1 ps jitter performance with loop bandwidths
between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided
down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device
provides virtually any frequency translation combination across this
operating range. The Si5324 input clock frequency and clock multiplication
ratio are programmable via an I2C or SPI interface. The Si5324 is based on
Silicon Laboratories' 3rd-generation DSPLL technology, which provides
any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter
performance optimization at the application level. The Si5324 is ideal for
providing clock multiplication and jitter attenuation in high performance
timing applications.
Generates any frequency from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 2 kHz to
710 MHz
Ultra-low jitter clock outputs as low
as 290 fs rms (12 kHz–20 MHz),
320 fs rms (50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(4– 525 Hz)
Meets ITU-T G.8251 and Telcordia
GR-253-CORE jitter specification
Hitless input clock switching with
phase build-out
Freerun, Digital Hold operation
Configurable signal format per
output (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236, 239/237, 66/64, 239/238,
15/14, 253/221, 255/238)
LOL, LOS, FOS alarm outputs
I2C or SPI programmable
On-chip voltage regulator with high
PSNR
Single supply 1.8 ±5%, 2.5 ±10%,
or 3.3 V ±10%
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS-compliant
Broadcast video –3G/HD/SD-SDI,
Genlock
Packet Optical Transport Systems
(P-OTS), MSPP
OTN/OTU-1/2/3/4 Asynchronous
Demapping (Gapped Clock)
SONET OC-48/192/768,
SDH/STM-16/64/256 line cards
1/2/4/8/10G Fibre Channel line
cards
GbE/10/40/100G Synchronous
Ethernet (LAN/WAN)
Data converter clocking
Wireless base stations
Test and measurement
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/
JITTER ATTENUATOR
Ordering Information:
See page 64.
Pin Assignments
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CK
IN
2+
CK
IN
2–
NC
RATE1
CK
IN
1+
CK
IN
1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1
NC
GN
D
VDD
NC
CKOUT2–
CKOUT2+
CM
ODE
GND
Pad
A0
GND
9
18
19
28
XB
LO
L
GND
CKOUT1+
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參數(shù)描述
SI5324D-C-GMR 功能描述:時鐘合成器/抖動清除器 Lo Loop BW Clk Multi Jitter Attn 2In/Out RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
SI5324E-C-GM 制造商:Silicon Laboratories Inc 功能描述:ANYRATE PRECISION CLOCK - Trays
Si5324-EVB 功能描述:時鐘和定時器開發(fā)工具 Si5324 Evaluation Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
SI5325 制造商:SILABS 制造商全稱:SILABS 功能描述:Pin-Controlled 1_710 MHz Jitter Cleaning Clock
Si5325/26-EVB 功能描述:時鐘和定時器開發(fā)工具 Si5325/Si5326 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V