參數(shù)資料
型號: IDT82V3011PVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/31頁
文件大?。?/td> 0K
描述: IC PLL WAN T1/E1/OC3 SGL 56-SSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: 電信
輸入: 時鐘
輸出: CMOS,LVDS,TTL
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 無/是
頻率 - 最大: 32.768MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: 82V3011PVG8
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-6237/5
1
May 24, 2006
T1/E1/OC3 WAN PLL WITH
SINGLE REFERENCE INPUT
IDT82V3011
FUNCTIONAL BLOCK DIAGRAM
TIE Control
Block
Input Frequency
Selection
F_sel0
F_sel1
Freerun
Normal Holdover
Fref
FLOCK
Invalid Input
Signal
Detection
MODE_sel0
MODE_sel1
TIE_en
Virtual
Reference
Feedback Signal
C16o
C8o
C4o
C2o
C3o
C1.5o
F0o
F8o
F16o
RSP
TSP
F19o
C6o
LOCK
F32o
C19POS
C19NEG
OSC
OSCi
TCLR
V
DDD
V
SS
V
SS
TDO TDI
JTAG
TMS
TRST
TCK
V
DDD
V
SS
V
DDD
V
DDA VSS
RST
State Control Circuit
Reference
Input Monitor
MON_out
C32o
C19o
DPLL
C2/C1.5
V
DDA VSS
FEATURES
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
4 Enhanced and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
MHz
Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
Provides a C2/C1.5 output clock signal with the frequency
controlled by the reference input Fref
Holdover frequency accuracy of 0.025 ppm
Phase slope of 5 ns per 125 s
Attenuates wander from 2.1 Hz
Fast lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
Input reference quality indication
3.3 V operation with 5 V tolerant I/O
Package available: 56-pin SSOP (Green option available)
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