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參數(shù)資料
| 型號： | IDT82V3011PVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN T1/E1/OC3 SGL 56-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 電信 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3011PVG8 |
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Functional Description
11
May 24, 2006
IDT82V3011
T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
2.5
TIE CONTROL BLOCK
If the input reference is badly damaged or lost, it is necessary to use
the reference generated by storage techniques instead. But when
changing the operating mode, a step change in phase on the input
reference will occur. A step change in phase in the DPLL input may lead
to an unacceptable phase change on the output signals. The TIE control
block, when enabled, prevents a step change in phase on the input
reference signal from causing a step change in phase on the output of
the DPLL block. Figure - 4 shows the TIE Control Block diagram.
Figure - 4 TIE Control Block Diagram
When the TIE Control Block is enabled manually or automatically (by
the TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit), it works under the control of the Step Generation circuit.
At the Measure Circuit stage, the input reference signal (Fref) is
compared with the feedback signal (current output feed back from the
Frequency Select Circuit). The phase difference between the input
reference and the feedback signal is stored in the Storage Circuit for TIE
correction. According to the value stored in the storage circuit, the
Trigger Circuit generates a virtual reference with the same phase as the
previous reference. In this way, the reference can be switched without
generating a step change in phase.
Figure - 5 shows the phase transient that will result if a mode change
is performed with the TIE Control Block enabled.
The value of the phase difference in the Storage Circuit can be
cleared by applying a logic low reset signal to the TCLR pin. The
minimum width of the reset pulse should be 300 ns.
When the IDT82V3011 primarily enters the Holdover mode for a
short time period and then returns back to the Normal mode, the TIE
Control Circuit should not be enabled. This will prevent undesired
accumulated phase change between the input and output.
If the TIE Control Block is disabled manually or automatically, a mode
change will result in a phase alignment between the input signal and the
output signal as shown in Figure - 6. The slope of the phase adjustment
is limited to 5 ns per 125 s.
Figure - 5 Reference Switch with TIE Control Block Enabled
Step Generation
TIE_en
Measure
Circuit
Storage
Circuit
Trigger Circuit
Feedback
Signal
TCLR
Fref
Virtual
Reference
Signal
Input Clock
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3012 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3012PV | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT82V3012PVG | 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDT82V3012PVG8 | 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3155 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS |
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