參數(shù)資料
型號(hào)： IDT82V3011PVG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 29/31頁(yè)
文件大?。?/td> 0K
描述： IC PLL WAN T1/E1/OC3 SGL 56-SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： 電信
輸入： 時(shí)鐘
輸出： CMOS，LVDS，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 1:12
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 32.768MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 56-SSOP
包裝： 帶卷 (TR)
其它名稱： 82V3011PVG8
Pin Description
7
May 24, 2006
IDT82V3011
T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
1
PIN DESCRIPTION
Name
Type
Pin Number
Description
VSS
Power
12, 18, 27
38, 47
Ground.
0 V. All VSS pins should be connected to the ground.
VDDA
Power
37, 48
3.3 V Analog Power Supply.
VDDD
Power
13, 19, 26
3.3 V Digital Power Supply.
OSCi
(CMOS) I
50
Oscillator Master Clock Input.
This pin is connected to a clock source.
Fref
I5
Reference Input.
This is the input reference source (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44 MHz)
used for synchronization. The frequency of the input reference can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.
This pin is internally pulled up to VDDD.
F_sel0
F_sel1
I
9
10
Frequency Selection Inputs.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input (Fref). See Table - 2 for details.
MODE_sel0
MODE_sel1
I
1
2
Mode Selection Inputs.
These two inputs determine the operating mode of the IDT82V3011 (Normal, Holdover or Freerun). See Table - 1 for
details.
The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down
to VSS.
RST
I4
Reset Input.
Pulling this pin to logic low for at least 300 ns will reset the IDT82V3011. While the RST pin is low, all framing and
clock outputs are at logic high.
To ensure proper operation, the device must be reset after it is powered up.
TCLR
I3
TIE Control Block Reset.
Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and
result in a realignment of the output phase with the input phase. This pin is internally pulled up to VDDD.
TIE_en
I56
TIE Control Block Enable.
A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this pin is gated
in by the rising edges of F8o. This pin is internally pulled down to Vss.
FLOCK
I45
Fast Lock Mode Enable.
If this pin is set to logic high, the DPLL will quickly lock to the input reference within 500 ms.
LOCK
(CMOS) O
44
Lock Indicator.
This output pin will go high when the DPLL is frequency locked to the input reference.
HOLDOVER
(CMOS) O
52
Holdover Indicator.
This output pin will go high whenever the DPLL enters Holdover mode.
NORMAL
(CMOS) O
46
Normal Indicator.
This output pin will go high whenever the DPLL enters Normal mode.
FREERUN
(CMOS) O
51
Freerun Indicator.
This output pin will go high whenever the DPLL enters Freerun mode.
MON_out
O
7
Frequency Out-of-range Indicator.
A logic high at this pin indicates that the reference input (Fref) is off the nominal frequency by more than ±12 ppm.
C19POS
C19NEG
(LVDS) O
21
22
19.44 MHz Clock Output (LVDS Level).
This pair of outputs is used for OC3/STS3 applications.
C19o
(CMOS) O
43
19.44 MHz Clock Output (CMOS Level).
This output is used for OC3/STS3 applications.
C32o
(CMOS) O
25
32.768 MHz Clock Output.
This output is a 32.768 MHz clock used for ST-BUS operation.
C16o
(CMOS) O
24
16.384 MHz Clock Output.
This output is a 16.384 MHz clock used for ST-BUS operation.
C8o
(CMOS) O
23
8.192 MHz Clock Output.
This output is an 8.192 MHz clock used for ST-BUS operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3012 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
IDT82V3012PV 制造商:Integrated Device Technology Inc 功能描述:
IDT82V3012PVG 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無(wú)/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
IDT82V3012PVG8 功能描述:IC PLL WAN T1/E1/OC3 DUAL 56SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3155 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
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