參數(shù)資料
型號: SI5324D-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 51/72頁
文件大?。?/td> 0K
描述: IC CLOCK MULT 2KHZ-150MHZ 36VQFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng)(WAN),SONET/SDH/STM,視頻
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 150MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5324
Rev. 1.1
55
Reset value = 0000 0000
Register 136.
Bit
D7
D6
D5D4D3
D2D1D0
Name
RST_REG
ICAL
Type
R/W
RR
RRRR
Bit
Name
Function
7
RST_REG
Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
6ICAL
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence.
ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-
tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)
must be present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-
bration, LOL will go low.
5:0
Reserved
Reserved.
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