- 您現在的位置：買賣IC網 > PDF目錄9576 > SI5319C-C-GM (Silicon Laboratories Inc)IC CLOCK MULT/ATTENUATOR 36QFN PDF資料下載
參數資料
| 型號： | SI5319C-C-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 8/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULT/ATTENUATOR 36QFN |
| 標準包裝： | 490 |
| 系列： | DSPLL® |
| 類型： | 時鐘/頻率倍增器，抖動衰減器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網，SONET/SDH |
| 輸入： | 時鐘，晶體 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 346MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-QFN（6x6） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
Si5319
16
Rev. 1.0
3. Functional Description
The Si5319 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock
source for frequency synthesis. The device provides virtually any frequency translation combination across this
operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I2C
or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine
the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes
phase noise and power consumption. This utility can be downloaded from http://www.silabs.com/timing.
The Si5319 is based on Silicon Laboratories' third generation DSPLL technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The Si5319 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz
to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input
clock frequency/clock multiplication ratio.
The Si5319 monitors the input clock for loss-of-signal and provides a LOS alarm when it detects missing pulses on
the input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously
monitoring the phase of the input clock in relation to the phase of the feedback clock.
The Si5319 provides a VCO freeze capability that allows the device to continue generation of a stable output clock
when the selected input reference is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XO
as its frequency reference.
The Si5319 has one differential clock output. The electrical format of the clock output is programmable to support
LVPECL, LVDS, CML, or CMOS loads. For system-level debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5,
or 3.3 V supply.
3.1. External Reference
A low-cost 114.285 MHz 3rd overtone crystal or an external reference oscillator is used as part of a fixed-frequency
oscillator within the DSPLL. This external reference is required for the device to operate. Silicon Laboratories
recommends using a high quality crystal. Specific recommendations may be found in the Family Reference
Manual. An external oscillator as well as other crystal frequencies can also be used as a reference for the device.
In VCO Freeze, the DSPLL remains locked to this external reference. Any changes in the frequency of this
reference when the DSPLL is in VCO freeze will be tracked by the output of the device. Note that crystals can have
temperature sensitivities.
3.2. Further Documentation
Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed
information about the Si5319. Additional design support is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration,
including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from
http://www.silabs.com/timing.
相關PDF資料 |
PDF描述 |
|---|---|
| VE-B24-MW-F4 | CONVERTER MOD DC/DC 48V 100W |
| VE-B22-MW-F2 | CONVERTER MOD DC/DC 15V 100W |
| MCZ33897DEF | IC TXRX SGL WIRE CAN 8-SOIC |
| MS3450L20-18PW | CONN RCPT 9POS WALL MNT W/PINS |
| VE-B20-MW-F3 | CONVERTER MOD DC/DC 5V 100W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SI5319C-C-GMR | 功能描述:時鐘合成器/抖動清除器 I2C/SPI-Program Prec Clk Xplier 1/1 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| Si5319-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5319 Eval Board RoHS:否 制造商:Texas Instruments 產品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI532 | 制造商:SILABS 制造商全稱:SILABS 功能描述:DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| SI5320 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| SI5320BC | 制造商:SILICON 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。