參數(shù)資料
型號(hào)： SI5319C-C-GM
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 36/50頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK MULT/ATTENUATOR 36QFN
標(biāo)準(zhǔn)包裝： 490
系列： DSPLL®
類型： 時(shí)鐘/頻率倍增器，抖動(dòng)衰減器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： 時(shí)鐘，晶體
輸出： CML，CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 346MHz
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 36-QFN（6x6）
包裝： 托盤
Si5319
Rev. 1.0
41
7
6
XB
XA
I
Analog
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Family Reference Manual for
interfacing to an external reference. The external reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crystal
or external clock is set by the RATE pins.
8, 31
19,20
GND
Supply
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11
15
RATE0
RATE1
I
3-Level
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not sup-
ported.
Note:
L setting corresponds to ground.
M setting corresponds to VDD/2.
H setting corresponds to VDD.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
16
17
CKIN+
CKIN–
IMulti
Clock Input.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
18
LOL
O
LVCMOS
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN
register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the
LOL_POL
bit. The PLL lock status will always be reflected in the
LOL_INT
read only register bit.
21
CS
I
LVCMOS
Xtal/Input Clock Select.
This pin selects the active DSPLL input clock, which can be a clock
input or a crystal input. See the FREE_EN register for free run settings.
0 = Select clock input (CKIN).
1 = Select crystal or external reference clock.
This pin should not be left open.
22
SCL
I
LVCMOS
Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and I2C modes.
This pin has a weak pull-down.
23
SDA_SDO
I/O
LVCMOS
Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial data
output.
Pin #
Pin Name
I/O
Signal Level
Description
Note:
Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
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