參數(shù)資料
型號: SI5319C-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 13/50頁
文件大?。?/td> 0K
描述: IC CLOCK MULT/ATTENUATOR 36QFN
標準包裝: 490
系列: DSPLL®
類型: 時鐘/頻率倍增器,抖動衰減器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: 時鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5319
20
Rev. 1.0
Register 2.
Reset value = 0100 0010
Reset value = 0000 0101
Bit
D7D6D5
D4
D3
D2D1D0
Name
BWSEL_REG [3:0]
Reserved
Type
R/W
R
Bit
Name
Function
7:4
BWSEL_REG
[3:0]
BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to take
effect.
3:0
Reserved
Reserved.
Register 3.
Bit
D7D6D5
D4D3
D2D1D0
Name
Reserved
VCO_
FREEZE
SQ_ICAL
Reserved
Type
RR/W
R/W
R
Bit
Name
Function
7:6
Reserved
Reserved.
5VCO_
FREEZE
VCO_FREEZE.
Forces the part into VCO Freeze. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force VCO Freeze mode. Overrides all other settings and ignores the quality of all of
the input clocks.
4
SQ_ICAL
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 9 on page 39.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0
Reserved
Reserved.
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