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參數(shù)資料
| 型號： | SI5100-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195PBGA |
| 標準包裝： | 119 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-LBGA |
| 供應商設備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤 |
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Si5100
Rev. 1.5
15
5.2.3. Slice Level Adjustment
The limiting amplifier allows adjustment of the 0/1
decision threshold, or slice level, to allow optimization of
bit-error-rates (BER) for demanding applications, such
as long-haul links. The Si5100 provides two different
modes of slice level adjustment: Absolute slice mode
and proportional slice mode. The mode is selected
using the SLICEMODE input.
In either mode, the slice level is set by applying a dc
voltage to the SLICELVL input. The mapping of the
voltage on the SLICELVL pin to the 0/1 decision
threshold voltage (or slice voltage) depends on the
selected mode of operation.
The SLICELVL mapping for absolute slice mode
(SLICEMODE = 0) is given in Figure 6. The linear
region of this curve can be approximated by the
following equation:
Equation 6
where VLEVEL is the effective slice level referred to the
RXDIN input, VSLICELVL is the voltage applied to the
SLICELVL pin, and VREF is the reference voltage
provided by the Si5100 on the VREF output pin
(nominally 1.25 V).
The SLICELVL mapping for proportional slice mode
(SLICEMODE = 1) is given in Figure 7 on page 18. The
linear region of this curve can be approximated by the
following equation:
Equation 7
where VLEVEL is the effective slice level referred to the
RXDIN input; VSLICELVL is the voltage applied to the
SLICELVL pin; VREF is the reference voltage provided
by the Si5100 on the VREF output pin, and VRXDIN(PP)
is the peak-to-peak voltage level of the receive data
signal applied to the RXDIN input.
The slice level adjustment function can be disabled by
tieing the SLICELVL input the VREF. When slice level
adjustment is disabled, the effective slice level is set to
0 mV relative to internally biased input common mode
voltage for RXDIN.
5.3. Clock and Data Recovery (CDR)
The Si5100 uses an integrated CDR to recover clock
and data from a non-return to zero (NRZ) signal input on
RXDIN. The recovered clock is used to regenerate the
incoming data by sampling the output of the limiting
amplifier at the center of the NRZ bit period.
5.3.1. Sample Phase Adjustment
In
applications
where
data
eye
distortions
are
introduced by the transmission medium, it may be
desirable to recover data by sampling at a point that is
not at the center of the data eye. The Si5100 provides a
sample
phase
adjustment
capability
that
allows
adjustment of the CDR sampling phase across the NRZ
data period. When sample phase adjustment is
enabled, the sampling instant used for data recovery
can be moved over a range of approximately ±22 ps
relative to the center of the incoming NRZ bit period.
The sample phase is set by applying a dc voltage to the
PHASEADJ input. The mapping of the voltage present
on the PHASEADJ input to the sample phase sampling
offset is given in Figure 8 on page 18. The linear region
of this curve can be approximated by the following
equation:
Equation 8
where
Phase
Offset
is
the
sampling
offset
in
picoseconds from the center of the data eye; VPHASEADJ
is the voltage applied to the PHASEADJ pin, and VREF
is the reference voltage provided by the Si5100 on the
VREF output pin (nominally 1.25 V). A positive phase
offset adjusts the sampling point to lead the default
sampling point (the aligned center of the data eye) and
a negative phase offset adjusts the sampling point to lag
the default sampling point.
Data recovery using a sampling phase offset is disabled
by tieing the PHASEADJ input to VREF. This forces a
phase offset of 0 ps to be used for data recovery.
5.3.2. Receiver Lock Detect
The Si5100 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. This circuit compares the frequency of a
divided down version of the recovered clock with the
frequency of the supplied reference clock. The Si5100
uses either REFCLK or TXCLK16IN as the reference
clock input signal depending on the state of the
REFSEL
input.
If
the
(divided)
recovered
clock
frequency deviates from that of the reference clock by
more than the amount specified in Table 5 on page 10,
the CDR is declared out of lock, and the loss-of-lock
(RXLOL) pin is asserted. In this state, the CDR attempts
to reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (RXCLK1
and RXCLK2) drifts over a range of approximately
±1000 ppm relative to the supplied reference clock
unless LTR is asserted. The RXLOL output remains
asserted until the frequency of the (divided) recovered
clock differs from the reference clock frequency by less
V
LEVEL
V
SLICELVL
VREF
0.4
–
0.375
0.005
–
V
LEVEL
V
SLICELVL
VREF
0.4
–
V
RXDIN PP
0.95
0.03
V
RXDIN PP
–
Phase Offset
85 ps/V
V
PHASEADJ
0.4
VREF
–
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