參數(shù)資料
型號(hào): SI3220PPT0-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 19/112頁
文件大?。?/td> 0K
描述: BOARD EVAL W/SI3200 INTERFACE
標(biāo)準(zhǔn)包裝: 1
系列: ProSLIC®
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: Si3220
已供物品: 板,CD
Si3220/25 Si3200/02
14
Rev. 1.3
Not
Recommended
fo
r N
ew
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esi
gn
s
Loop Voltage Sense Accuracy
Accuracy of boundaries for
each output code;
VTIP – VRING =48V
—±2
±4
%
Loop Current Sense Accuracy
Accuracy of boundaries for
each output code;
ILOOP =18mA
—±7
±10
%
Power Alarm Threshold Accuracy
Power Threshold = 300 mW
±25
%
Table 7. Monitor ADC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Resolution
8
Bits
Differential Nonlinearity
DNL
–1.0
±0.75
+1.5
LSB
Integral Nonlinearity
INL
±0.6
±1.5
LSB
Gain Error
±0.1
±0.25
LSB
Table 6. Linefeed Characteristics (Continued)
(VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Adaptive linefeed is enabled when the VOCDELTA RAM address is set to a non-zero value and is disabled when
VOCDELTA is set to 0.
2. RDC,MAX is the maximum dc resistance of the CPE; hence the specified total loop resistance is RLOOP + RDC,MAX.
3. Ringing amplitude is set for 93 V peak using the RINGAMP RAM address and measured at TIP-RING using no series
protection resistance.
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