參數(shù)資料
型號： SI3211PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 97/148頁
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3211
已供物品： 板，CD
Si3210/Si3211
52
Rev. 1.61
Not
Recommended
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path and ends with an analog signal at the output of
the receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 25.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows testing of the analog signal
processing circuitry of the Si3210 to be carried out
completely independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path are fed back
to the input of the transmit path by way of the hybrid
filter path. (See Figure 25.) The signal path starts
with 8-bit PCM data input to the receive path and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and interface directly to the 16-bit data.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3210 to be carried
out completely independently of any analog signal
processing activity. The user can bypass the
companding process and interface directly to the 16-
bit data.
2.8. Two-Wire Impedance Matching
The ProSLIC provides on-chip, programmable, two-wire
impedance settings to meet a wide variety of worldwide
two-wire
return
loss
requirements.
The
two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600
will be loaded into the TISS
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC), a
switched
capacitor
network
(XAC),
and
a
transconductance amplifier (Gm). (See Figure 25.) RAC
creates the real portion, and XAC creates the imaginary
portion of Gm’s input. Gm then creates a current that
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer, IBUF, which is implemented using
transistors Q1 and Q2 (see Figure 13 on page 24). Gm
is referenced to an off-chip resistor (R15).
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
Silicon revisions C and higher support the option to
remove
the
internal
reference
resistor
used
to
synthesize ac impedances for 600 + 2.16 F and
900 + 2.16 F settings so that an external resistor
reference may be used. This option is enabled by
setting ZSEXT = 1 (direct Register 108, bit 4).
2.9. Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or
8.192 MHz. (Note that 768 kHz and 1.536 MHz are not
valid rates for GCI mode.) The ratio of the PCLK rate to
the FSYNC rate is determined via a counter clocked by
PCLK. The three-bit ratio information is automatically
transferred
into
an
internal
register,
PLL_MULT,
following a reset of the ProSLIC. The PLL_MULT is
used to control the internal PLL, which multiplies PCLK
as needed to generate the 16.384 MHz rate needed to
run the internal filters and other circuitry.
The PLL clock synthesizer settles very quickly following
powerup. However, the settling time depends on the
PCLK frequency, and it can be approximated by the
following equation:
2.10. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Loop current/ring ground detected
Ring trip detected
Power alarm
DTMF digit detected
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
T
SETTLE
64
F
PCLK
-----------------
=
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