參數(shù)資料
型號(hào)： SI3211PPTX-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 77/148頁
文件大?。?/td> 0K
描述： BOARD EVAL W/DISCRETE INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： Si3211
已供物品： 板，CD
Si3210/Si3211
34
Rev. 1.61
Not
Recommended
fo
r N
ew
D
esi
gn
s
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
Table 25. Associated Power Monitoring and Power Fault Registers
Parameter
Description/ Range
Resolution
Register
Bits
Location*
Power Monitor Pointer
0 to 5 points to Q1 to
Q6, respectively
n/a
PWRMP[2:0]
Direct Register 76
Line Power Monitor Output
0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3, Q4
30.4 mW
3.62 mW
PWROM[7:0]
Direct Register 77
Power Alarm Threshold, Q1 & Q2
0 to 7.8 W
30.4 mW
PPT12[7:0]
Indirect Register 32
Power Alarm Threshold, Q3 & Q4
0 to 0.9 W
3.62 mW
PPT34[7:0]
Indirect Register 33
Power Alarm Threshold, Q5 & Q6
0 to 7.8 W
30.4 mW
PPT56[7:0]
Indirect Register 34
Thermal LPF Pole, Q1 & Q2
See equation above.
NQ12[7:0]
Indirect Register 37
Thermal LPF Pole, Q3 & Q4
See equation above.
NQ34[7:0]
Indirect Register 38
Thermal LPF Pole, Q5 & Q6
See equation above.
NQ56[7:0]
Indirect Register 39
Power Alarm Interrupt Pending
Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
n/a
QnAP[n+1],
where n = 1
to 6
Direct Register 19
Power Alarm Interrupt Enable
Bits 2 to 7 correspond
to Q1 to Q6, respec-
tively
n/a
QnAE[n+1],
where n = 1
to 6
Direct Register 22
Power Alarm
Automatic/Manual Detect
0 = manual mode
1 = enter open state
upon power alarm
n/a
AOPN
Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
PPT56
P
MAX
Resolution
-------------------------------
2
7
1.28
0.0304
------------------
2
7
5389
150Dh
==
=
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