
Si3210/Si3211
118
Rev. 1.61
Not
Recommended
fo
r N
ew
D
esi
gn
s
4. Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A
write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the
contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.
A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the
value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of
16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an
interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
4.1. DTMF Decoding
All values are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 37. DTMF Indirect Registers Summary
Addr.
D15
D14
D13
D12
D11
D10
D9D8D7D6D5
D4D3D2D1D0
0
ROW0[15:0]
1
ROW1[15:0]
2
ROW2[15:0]
3
ROW3[15:0]
4
COL[15:0]
5
FWDTW[15:0]
6
REVTW[15:0]
7
ROWREL[15:0]
8
COLREL[15:0]
9
ROW2[15:0]
10
COL2[15:0]
11
PWRMIN[15:0]
12
HOTL[15:0]