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| 型號： | SI3056DC-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 31/94頁 |
| 文件大小： | 0K |
| 描述： | DAUGHTERCARD DAA SI3056/SI3018 |
| 標準包裝： | 1 |
| 主要目的： | 電信，數(shù)據(jù)采集裝置（DAA） |
| 已用 IC / 零件： | Si3056 |
| 已供物品： | 板，CD |
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Si3056
Si3018/19/10
Rev. 1.05
37
5.25.2. PLL Lock Times
The Si3056 changes sample rates quickly. However,
lock time varies based on the programming of the clock
generator. The following relationships describe the
boundaries on PLL locking time:
PLL1 lock time < 1 ms
PLL2 lock time 100
s to 1 ms
For
modem
designs,
Silicon
Laboratories
recommends that PLL1 be programmed during
initialization. No further programming of PLL1 is
necessary. The SRC[3:0] register can be programmed
for the required initial sample rate, typically 7200 Hz.
Rate changes are made by writing to SRC[3:0]
(Register 7, bits 3:0).
The final design consideration for the clock generator is
the update rate of PLL1. The following criteria must be
satisfied for the PLLs to remain stable:
Figure 26. Update Rate of PLL1
5.26. Digital Interface
The Si3056 has two serial interface modes that support
most standard modem DSPs. The M0 and M1 mode
pins select the interface mode. The key difference
between these two serial modes is the operation of the
FSYNC signal. Table 21 summarizes the serial mode
definitions.
The digital interface consists of a single, synchronous
serial link that communicates both telephony and
control data.
In serial mode 0 or 1, the Si3056 operates as a master,
where the master clock (MCLK) is an input, the serial
data clock (SCLK) is an output, and the frame sync
signal (FSYNC) is an output. The MCLK frequency and
the value of the sample rate control registers 7, 8, and 9
determine the sample rate (Fs). The serial port clock,
SCLK, runs at 256 bits per frame, where the frame rate
is equivalent to the sample rate. See "5.25.Clock
Generation" on page 36 for details on programming
sample rates.
The Si3056 transfers 16- or 15-bit telephony data in the
primary timeslot and 16-bit control data in the secondary
the serial frames. Primary frames occur at the frame
rate and are always present. To minimize overhead in
the external DSP, secondary frames are present only
when requested.
Two methods exist for requesting a secondary frame to
transfer control information. The default powerup mode
uses the LSB of the 16-bit transmit (TX) data word as a
flag to request a secondary transfer. Only 15-bit TX data
is transferred, which results in a small loss of SNR but
FUP1
FMCLK
N
-------------------
=
144 kHz
≥
DIV
8-bit
PLL1
DIV
N2
DIV
3
DIV
16
PLL2
DIV
8-bit
DIV
M2
Decoder
1
0
01
SCLK
F
UP1
98.304 MHz
32.768 MHz
N1
M1
Slave
SRATE
MCLK
Table 21. Serial Modes
Mode
M1 M0
Description
0
0 0
FSYNC frames data
1
0 1
FSYNC pulse starts data frame
2
1 0
Slave mode
3
1 1
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si3056-D-FS | 功能描述:電信線路管理 IC Si3056 DAA System Side SSI Interface RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3056-D-FSR | 功能描述:電信線路管理 IC Si3056 DAA System Side SSI Interface RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| SI3056-D-ZS3R | 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET 56KBPS - Tape and Reel |
| SI3056-F-FS | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3056-FS | 功能描述:IC SYSTEM-SIDE DAA 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 調(diào)制解調(diào)器 - IC 和模塊 系列:- 標準包裝:25 系列:- 數(shù)據(jù)格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 電源電壓:3.3V 安裝類型:- 封裝/外殼:- 供應(yīng)商設(shè)備封裝:- 包裝:托盤 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名稱:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
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