參數(shù)資料
型號: SI3050-E1-GT
廠商: Silicon Laboratories Inc
文件頁數(shù): 79/128頁
文件大?。?/td> 0K
描述: IC VOICE DAA SYSTEM SIDE 24QFN
標(biāo)準(zhǔn)包裝: 74
系列: *
Si3050 + Si3011/18/19
54
Rev. 1.5
The data presented to the Si3050 in the downstream Monitor bits must be present for two consecutive frames to be
considered valid data. The Si3050 checks to ensure it receives the same data in two consecutive frames. If not, it
does not acknowledge receipt of the data byte and waits until it does receive two consecutive identical data bytes
before acknowledging to the transmitter that it received the data. If the transmitter attempts to signal transmission
of a subsequent data byte by placing the downstream MX bit in an inactive state while the Si3050 is still waiting to
receive a valid data byte transmission of two consecutive identical data bytes, the Si3050 signals an abort and
ends the transmission. Figure 45 shows a state diagram for the Receiver Monitor channel for the Si3050. Figure 46
on page 55 shows a state diagram for the Transmitter Monitor channel for the Si3050.
Figure 45. Si3050 Monitor Receiver State Diagram
MX
MX x LL
Initial
State
Any
State
MX
x
L
ABT
MR: MR bit calculated and transmitted on DTX line.
MX: MX bit received data downstream (DRX line).
LL: Last look of monitor byte received on DRX line.
ABT: Abort indication to internal source.
MX
nth Byte
received
MR = 1
New Byte
MR = 1
Byte
Valid
MR = 0
1st Byte
Received
MR = 0
Abort
MR = 1
Wait
for LL
MR = 0
Wait
for LL
MR = 0
Idle
MR = 1
MX x LL
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