參數(shù)資料
型號(hào): SI3050-E1-GT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 75/128頁(yè)
文件大小: 0K
描述: IC VOICE DAA SYSTEM SIDE 24QFN
標(biāo)準(zhǔn)包裝: 74
系列: *
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Si3050 + Si3011/18/19
50
Rev. 1.5
Figure 42. Read Operation via a 16-bit SPI Port
Figures 41 and 42 illustrate WRITE and READ
operations via a 16-bit SPI controller. These operations
require a 4-byte transfer arranged as two 16-bit words.
The CS pin does not go high when the eighth bit of data
is received, which indicates to the SPI state machine
that eight more SCLK pulses follow to complete the
operation. In the case of a WRITE operation, the last
eight bits are ignored. In a read operation, the 8-bit data
value is repeated so that the data may be captured
during the last half of a data transfer if required by the
controller. The Si3050 autodetects the SPI mode (16-bit
or 8-bit mode).
5.36. GCI Highway
The Si3050 contains an alternate communication
interface to the SPI and PCM highway control and data
interface. The general circuit interface (GCI) can be
used for the transmission and reception of control and
data information onto a GCI highway bus. The PCM and
GCI highways are 4-wire interfaces and share the same
pins. The SPI control interface is not used as a
communication interface in the GCI highway mode, but
rather as hardwired channel selector pins.
When GCI mode is selected, the sub-frame selection
pins must be tied to the correct state to select one of
eight sub-frame timeslots in the GCI frame (Table 24).
These pins must remain in this state when the Si3050 is
operating. Selecting a particular subframe automatically
causes that individual Si3050 to transmit and receive on
the appropriate sub-frame in the GCI frame, which is
initiated by an FSYNC pulse. No more register settings
are needed to select which sub-frame a device uses,
and the sub-frame for a particular device cannot be
changed when in operation. Only one Si3050 DAA can
be assigned per sub-frame, which allows a total of eight
DAAs to be connected to the same GCI highway bus.
GCI mode supports a 1x and a 2x PCLK rate as shown
in Figures 5 and 6 on pages 13 and 14, respectively.
The PCLK rate is autodetected and no internal register
settings are needed to support either 1x or 2x PCLK
mode.
The GCI highway requires either a 2.048 or 4.096 MHz
clock frequency on the PCLK pin, and an 8 kHz frame
sync input on the FSYNC pin. The overall unit of data
used to communicate on the GCI highway is a frame,
which is 125 s in length. Each frame is initiated by a
pulse on the FSYNC pin and the rising edge signifies
the beginning of the next frame. In 2x PCLK mode,
there are twice as many PCLK cycles during each
125 s frame versus 1x PCLK mode. Each frame
consists of eight fixed timeslot sub-frames that are
assigned using the Sub-Frame Select pins as described
in Table 21 on page 40 (SDI_THRU, SDO, and CS).
Within each sub-frame are four channels (bytes) of
data, including the two voice data channels (B1 and
B2), one Monitor channel (M) for initialization and setup
of the device, and one Signaling and Control channel
X X X X X X X X
CS B
SCLK
SDI
SDO
Data [7:0]
CONTROL
A DDRE S S
X X X X X X X X
Data [7:0]
S am e by te repeated twic e.
Table 24. GCI Mode Sub-Frame Selection
SDI_THRU SDO
CS
GCI Subframe 0 Selected
(Voice channels 1–2)
11
1
GCI Subframe 1 Selected
(Voice channels 3–4)
11
0
GCI Subframe 2 Selected
(Voice channels 5–6)
10
1
GCI Subframe 3 Selected
(Voice channels 7–8)
10
0
GCI Subframe 4 Selected
(Voice channels 9–10)
01
1
GCI Subframe 5 Selected
(Voice channels 11–12)
01
0
GCI Subframe 6 Selected
(Voice channels 13–14)
00
1
GCI Subframe 7 Selected
(Voice channels 15–16)
00
0
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