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參數(shù)資料
| 型號： | SCAN921226SLC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | LINE RECEIVER, PBGA49 |
| 封裝： | FBGA-49 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 474K |
| 代理商： | SCAN921226SLC |
Deserializer Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t
HZR
HIGH to TRI-STATE
Delay
t
LZR
LOW to TRI-STATE
Delay
t
ZHR
TRI-STATE to HIGH
Delay
t
ZLR
TRI-STATE to LOW
Delay
t
DSR1
Deserializer PLL Lock
Time from PWRDWN
(with SYNCPAT)
(Note 7)
t
DSR2
Deserializer PLL Lock
time from SYNCPAT
Pin/Freq.
Rout(0-9)
Min
Typ
Max
Units
Figure 14
2.8
10
ns
2.8
10
ns
4.2
10
ns
4.2
10
ns
Figure 15
Figure 16
30MHz
1.7
3.5
μs
80MHz
1.0
2.5
μs
30MHz
80MHz
0.65
0.29
1.5
0.8
μs
μs
t
ZHLK
TRI-STATE to HIGH
Delay (power-up)
Ideal Noise Margin
Right
Ideal Noise Margin Left
LOCK
3.7
12
ns
t
RNMI-R
Figure 20
80 MHz
+350
ps
t
RNMI-L
Figure 20
80 MHz
-385
ps
SCAN Circuitry Timing Requirements
Symbol
f
MAX
Parameter
Conditions
Min
25.0
Typ
50.0
Max
Units
MHz
Maximum TCK Clock
Frequency
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to TCK
R
L
= 500
, C
L
= 35 pF
t
S
t
H
t
S
t
H
t
W
t
W
t
REC
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,
VOD,
VTH and VTL which are differential voltages.
Note 4:
t
LLHT
and t
LHLT
specifications are Guaranteed By Design (GBD) using statistical analysis.
Note 5:
Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 6:
t
DJIT
specifications are Guaranteed By Design using statistical analysis.
Note 7:
For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and with specific
conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either t
timing or t
timing. t
is the
time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. t
is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from
not receiving data to receiving synchronization patterns (SYNCPATs).
Note 8:
t
is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
1.0
2.0
2.5
1.5
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
S
www.national.com
8
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| SCAN921226SLC/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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