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參數(shù)資料
| 型號： | SCAN921226SLC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | LINE RECEIVER, PBGA49 |
| 封裝： | FBGA-49 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 474K |
| 代理商： | SCAN921226SLC |
Block Diagrams
(Continued)
Functional Description
The SCAN921025 and SCAN921226 are a 10-bit Serializer
and Deserializer chipset designed to transmit data over dif-
ferential backplanes at clock speeds from 30 to 80 MHz. The
chipset is also capable of driving data over Unshielded
Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initializa-
tion, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE. In addition to the active
and passive states, there are also test modes for JTAG
access and at-speed BIST.
The following sections describe each operation and passive
state and the test modes.
Initialization
Initialization of both devices must occur before data trans-
mission begins. Initialization refers to synchronization of the
Serializer and Deserializer PLL’s to local clocks, which may
be the same or separate. Afterwards, synchronization of the
Deserializer to Serializer occurs.
Step 1: When you apply V
CC
to both Serializer and/or Dese-
rializer, the respective outputs enter TRI-STATE, and on-chip
power-on circuitry disables internal circuitry. When V
CC
reaches V
OK (2.5V) the PLL in each device begins lock-
ing to a local clock. For the Serializer, the local clock is the
transmit clock (TCLK) provided by the source ASIC or other
device. For the Deserializer, you must apply a local clock to
the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer is
now ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs or a data stream.
The SYNC pattern sent by the Serializer consists of six ones
and six zeros switching at the input clock rate.
Note that the Deserializer LOCK output will remain high
while its PLL locks to the incoming data or to SYNC patterns
on the input.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete initialization. The Deserializer will lock to
non-repetitive data patterns. However, the transmission of
SYNC patterns enables the Deserializer to lock to the Seri-
alizer signal within a specified time. See Figure 9
The user’s application determines control of the SYNC1 and
SYNC 2 pins. One recommendation is a direct feedback loop
from the LOCK pin. Under all circumstances, the Serializer
stops sending SYNC patterns after both SYNC inputs return
low.
When the Deserializer detects edge transitions at the Bus
LVDS input, it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low, the
Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs
DIN0–DIN9. The Serializer uses the TCLK input to latch
incoming Data. The TCLK_R/F pin selects which edge the
Serializer uses to strobe incoming data. TCLK_R/F high
selects the rising edge for clocking data and low selects the
falling edge. If either of the SYNC inputs is high for 5*TCLK
cycles, the data at DIN0-DIN9 is ignored regardless of clock
edge.
After determining which clock edge to use, a start and stop
bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low.
The start and stop bits function as the embedded clock bits
in the serial stream.
The Serializer transmits serialized data and clock bits (10+2
bits) from the serial data output (DO
±
) at 12 times the TCLK
frequency. For example, if TCLK is 80 MHz, the serial rate is
80 x 12 = 960 Mega-bits-per-second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 80 MHz, the pay-
load data rate is 80 x 10 = 800 Mbps. The data source
provides TCLK and must be in the range of 30 MHz to 80
MHz nominal.
The Serializer outputs (DO
±
) can drive a point-to-point con-
nection or in limited multi-point or multi-drop backplanes.
The outputs transmit data when the enable pin (DEN) is
high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the Serializer output pins will enter
TRI-STATE.
When the Deserializer synchronizes to the Serializer, the
LOCK pin is low. The Deserializer locks to the embedded
Application
DS200248-2
S
www.national.com
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921226SLC/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN921260 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921260UJB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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