參數(shù)資料
型號(hào): SCAN921226SLC
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): 通用總線功能
英文描述: 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述: LINE RECEIVER, PBGA49
封裝: FBGA-49
文件頁(yè)數(shù): 19/21頁(yè)
文件大?。?/td> 474K
代理商: SCAN921226SLC
Serializer Pin Description
Pin Name
I/O
I
Ball Id.
A3, B1, C1,
D1, D2, D3,
E1, E2, F2,
F4
G3
Description
DIN
Data Input. LVTTL levels inputs. Data on these pins are loaded
into a 10-bit input register.
TCLKR/F
I
Transmit Clock Rising/Falling strobe select. LVTTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
+ Serial Data Output. Non-inverting Bus LVDS differential output.
Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. LVTTL level input. A low puts the Bus
LVDS outputs in TRI-STATE.
Powerdown. LVTTL level input. PWRDN driven low shuts down
the PLL and TRI-STATEs outputs putting the device into a low
power sleep mode.
Transmit Clock. LVTTL level input. Input for 30MHz – 80MHz
system clock.
Assertion of SYNC (high) for at least 1024 synchronization
symbols to be transmitted on the Bus LVDS serial output.
Synchronization symbols continue to be sent if SYNC continues to
be asserted. TTL level input. The two SYNC pins are ORed.
Digital Circuit power supply.
Digital Circuit ground.
DO+
DO
DEN
O
O
I
D7
D5
D6
PWRDN
I
C7
TCLK
I
E4
SYNC
I
A4, B3
DVCC
DGND
I
I
C3, C4, E5
A1, C2, F5,
E6, G4
A5, A6, B4,
B7, G5
B5, B6, C6,
E7, F7
F1
AVCC
I
Analog power supply (PLL and Analog Circuits).
AGND
I
Analog ground (PLL and Analog Circuits).
TDI
I
Test Data Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1. There is an
internal pullup resistor that defaults this input to high per IEEE
1149.1.
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
Leave open circuit, do not connect
TDO
TMS
O
I
G1
E3
TCK
TRST
I
I
F3
G2
N/C
N/A
A2, A7, B2,
C5, D4, F6,
G6, G7
S
www.national.com
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