參數(shù)資料
型號： SCAN921226SLC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
中文描述： LINE RECEIVER, PBGA49
封裝： FBGA-49
文件頁數(shù)： 7/21頁
文件大?。?/td> 474K
代理商： SCAN921226SLC
Serializer Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
t
DIS
DIN (0-9) Setup to TCLK
t
DIH
DIN (0-9) Hold from
TCLK
t
HZD
DO
±
HIGH to
TRI-STATE Delay
t
LZD
DO
±
LOW to
TRI-STATE Delay
t
ZHD
DO
±
TRI-STATE to
HIGH Delay
t
ZLD
DO
±
TRI-STATE to
LOW Delay
t
SPW
SYNC Pulse Width
t
PLD
Serializer PLL Lock Time
t
SD
Serializer Delay
Conditions
Min
0
Typ
Max
Units
ns
R
L
= 27
,
C
L
=10pF to GND
Figure 7
4.0
ns
R
L
= 27
,
C
L
=10pF to GND
Figure 8
(Note 5)
3
10
ns
3
10
ns
5
10
ns
6.5
10
ns
R
L
= 27
Figure 10
5*t
TCP
510*t
TCP
t
TCP
+
1.0
ns
ns
513*t
TCP
t
TCP
+
3.5
R
L
= 27
, Figure 11
t
TCP
+
2.5
ns
t
DJIT
Deterministic Jitter
R
L
=
27
,
C
L
=10pF
to GND,
(Note 6)
80 MHz
-130
-40
+60
ps
t
RJIT
Random Jitter
6
10
ps
(RMS)
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
t
RFCP
REFCLK Period
t
RFDC
REFCLK Duty Cycle
t
RFCP
/ t
TCP
Ratio of REFCLK to TCLK
t
RFTT
REFCLK Transition Time
Conditions
Min
12.5
30
95
Typ
T
50
1
3
Max
33.3
70
105
6
Units
ns
%
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t
RCP
Receiver out Clock
Period
Figure 11
t
CLH
CMOS/TTL Low-to-High
Transition Time
Figure 5
Pin/Freq.
Min
Typ
Max
Units
t
RCP
= t
TCP
RCLK
12.5
33.3
ns
CL = 15 pF
Rout(0-9),
LOCK,
RCLK
1.2
4
ns
t
CHL
CMOS/TTL High-to-Low
Transition Time
Deserializer Delay
Figure 12
1.1
4
ns
t
DD
All Temp./ All Freq.
Room Temp./3.3V/30MHz
Room Temp./3.3V/80MHz
1.75*t
RCP
+1.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.5
1.75*t
RCP
+2.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.0
1.75*t
RCP
+2.25 1.75*t
RCP
+5.0 1.75*t
RCP
+8.0
ns
ns
ns
t
ROS
ROUT Data Valid before Figure 13
RCLK
RCLK
30MHz
0.4*t
RCP
0.5*t
RCP
ns
RCLK
80MHz
0.35*t
RCP
0.5*t
RCP
ns
t
ROH
ROUT Data valid after
RCLK
RCLK Duty Cycle
Figure 13
30MHz
80MHz
0.4*t
RCP
0.35*t
RCP
45
0.5*t
RCP
0.5*t
RCP
50
ns
ns
%
t
RDC
55
S
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