參數(shù)資料
型號(hào): SC16IS750IPW
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁(yè)數(shù): 51/62頁(yè)
文件大?。?/td> 308K
代理商: SC16IS750IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
51 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 40.
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
V
DD
= 2.5 V
±
0.2 V T
amb
=
40
°
C to +85
°
C; or V
DD
= 3.3 V
±
0.3 V T
amb
=
40
°
C to +95
°
C and refer to V
IL
and V
IH
with
an input voltage of V
SS
to V
DD
. All output load = 25 pF unless otherwise specified.
Symbol
Parameter
Conditions
SC16IS760 SPI-bus timing specifications
V
DD
= 2.5 V
Min
V
DD
= 3.3 V
Min
Unit
Max
Max
t
TR
t
CSS
t
CSH
t
DO
t
DS
t
DH
t
CP
t
CH
t
CL
t
CSW
t
d9
t
d10
t
d11
t
d12
t
d13
t
d14
t
w(rst)
CS HIGH to SO 3-state delay time
CS to SCLK setup time
CS to SCLK hold time
SCLK fall to SO valid delay time
SI to SCLK setup time
SI to SCLK hold time
SCLK period
SCLK HIGH time
SCLK LOW time
CS HIGH pulse width
SPI output data valid time
SPI modem output data valid time
SPI transmit interrupt clear time
SPI modem input interrupt clear time
SPI interrupt clear time
SPI receive interrupt clear time
reset pulse width
C
L
= 100 pF
-
100
5
-
10
10
83
30
30
200
200
200
200
200
200
200
3
100
-
-
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
5
-
10
10
67
25
25
200
200
200
200
200
200
200
3
100
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
C
L
= 100 pF
t
CL
+ t
CH
Fig 34. Detailed SPI-bus timing
t
CSH
t
CSS
t
CL
t
CH
t
CSH
t
DO
t
TR
t
DS
t
DH
SO
SI
SCLK
CS
002aab066
t
CSW
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