參數(shù)資料
型號(hào)： SC16IS750IPW
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 連接器件
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝： SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁(yè)數(shù)： 35/62頁(yè)
文件大?。?/td> 308K
代理商： SC16IS750IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
35 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.20 Extra Features Control Register (EFCR)
[1]
For SC16IS760 only.
9.
RS-485 features
9.1 Auto RS-485 RTS control
Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin
(logic 1) once the last bit of the data has been transmitted.
To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.
Table 31.
Bit
7
Extra Features Control Register bits description
Symbol
Description
IRDA MODE
IrDA mode
0 = IrDA SIR,
3
16
pulse ratio, data rate up to 115.2 kbit/s
1 = IrDA SIR,
1
4
pulse ratio, data rate up to 1.152 Mbit/s
[1]
-
reserved
RTSINVER
invert RTS signal in RS-485 mode
0: RTS = 0 during transmission and RTS = 1 during reception
1: RTS = 1 during transmission and RTS = 0 during reception
RTSCON
enable the transmitter to control the RTS pin
0 = transmitter does not control RTS pin
1 = transmitter controls RTS pin
-
reserved
TXDISABLE
Disable transmitter. UART does not send serial data out on the
transmit pin, but the transmit FIFO will continue to receive data from
host until full. Any data in the TSR will be sent out before the
transmitter goes into disable state.
0: transmitter is enabled
1: transmitter is disabled
RXDISABLE
Disable receiver. UART will stop receiving data immediately once this
bit set to a 1, and any data in the TSR will be sent to the receive FIFO.
User is advised not to set this bit during receiving.
0: receiver is enabled
1: receiver is disabled
9-BIT MODE
Enable 9-bit or Multidrop mode (RS-485).
0: normal RS-232 mode
1: enables RS-485 mode
6
5
4
3
2
1
0
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