參數(shù)資料
型號: SC16IS750IPW
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù): 38/62頁
文件大?。?/td> 308K
代理商: SC16IS750IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
38 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There are two exceptions to the ‘a(chǎn)cknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by
not
signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
10.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
Fig 18. Data transfer on the I
2
C-bus
S
P
SDA
SCL
MSB
0
1
6
7
8
0
1
2 to 7
8
ACK
ACK
002aab012
START
condition
STOP
condition
acknowledgement signal
from receiver
byte complete,
interrupt within receiver
clock line held LOW
while interrupt is serviced
Fig 19. Acknowledge on the I
2
C-bus
S
0
1
6
7
8
002aab013
data output
by transmitter
data output
by receiver
SCL from master
START
condition
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
相關(guān)PDF資料
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SC16IS750IPW,128 功能描述:UART 接口集成電路 I2C/SPI-UARTBRIDGE W/IRDA AND GPIO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS750IPW-S 功能描述:IC UART I2C/SPI 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - UART(通用異步接收器/發(fā)送器) 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 特點(diǎn):* 通道數(shù):2,DUART FIFO's:16 字節(jié) 規(guī)程:RS232,RS485 電源電壓:2.25 V ~ 5.5 V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP(7x7) 包裝:托盤 其它名稱:XR16L2551IM-F-ND
SC16IS750IPW-T 功能描述:IC UART I2C/SPI 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - UART(通用異步接收器/發(fā)送器) 系列:- 標(biāo)準(zhǔn)包裝:490 系列:- 特點(diǎn):可編程 通道數(shù):1,UART FIFO's:128 字節(jié) 規(guī)程:RS485 電源電壓:1.8V 帶并行端口:- 帶自動流量控制功能:是 帶IrDA 編碼器/解碼器:是 帶故障啟動位檢測功能:是 帶調(diào)制解調(diào)器控制功能:是 帶CMOS:是 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-HVQFN(5x5) 包裝:托盤 產(chǎn)品目錄頁面:828 (CN2011-ZH PDF) 其它名稱:568-4707935286785151SC16C850SVIBS-S
SC16IS752 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support