參數(shù)資料
型號(hào)： SC16IS750IPW
廠商： NXP Semiconductors N.V.
元件分類： 連接器件
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝： SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù)： 31/62頁
文件大?。?/td> 308K
代理商： SC16IS750IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
31 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.10 Enhanced Features Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART.
Table 22
shows
the enhanced feature register bit settings.
8.11 Division registers (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Remark:
DLL and DLH can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Table 22.
Bit
7
Enhanced Features Register bits description
Symbol
Description
EFR[7]
CTS flow control enable
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
EFR[6]
RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the
receiver FIFO
halt
trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO
resume
transmission trigger level TCR[7:4] is reached.
EFR[5]
Special character detect
logic 0 = Special character detect disabled (normal default condition)
logic 1 = Special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to FIFO
and IIR[4] is set to a logical 1 to indicate a special character has been
detected.
EFR[4]
Enhanced functions enable bit
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
so that they can be modified.
EFR[3:0]
Combinations of software flow control can be selected by programming these
bits. See
Table 3 “Software flow control options (EFR[3:0])”
.
6
5
4
3:0
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