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參數(shù)資料
| 型號(hào)： | SC16IS740IPW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 連接器件 |
| 英文描述： | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| 封裝： | SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1. |
| 文件頁數(shù)： | 26/62頁 |
| 文件大?。?/td> | 308K |
| 代理商： | SC16IS740IPW |
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SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
26 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.5 Line Status Register (LSR)
Table 16
shows the Line Status Register bit settings.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Table 16.
Bit
7
Line Status Register bits description
Symbol
Description
LSR[7]
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = transmit hold register is not empty
logic 1 = transmit hold register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
LSR[4]
break interrupt
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated character is 0x00, that
is, RX was LOW for one character time frame
LSR[3]
framing error
logic 0 = no framing error in data being read from RX FIFO (normal default
condition).
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
LSR[2]
parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
LSR[1]
overrun error
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
LSR[0]
data in receiver
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
6
5
4
3
2
1
0
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| SC16IS750IBS | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| SC16IS750IPW | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
| SC16IS760IBS | Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16IS740IPW,112 | 功能描述:UART 接口集成電路 UART SINGLE W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS740IPW,128 | 功能描述:UART 接口集成電路 I2C/SPI-SLAVEBRIDGE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS740IPW/Q900, | 功能描述:UART 接口集成電路 I2C/SPI-UART BRIDGE W/IRDA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16IS740IPW/Q900,128 | 制造商:NXP Semiconductors 功能描述:0 |
| SC16IS740IPW112 | 制造商:NXP Semiconductors 功能描述:IC SINGLE UART FIFO 5MBPS 3.6V TSSOP-16 制造商:NXP Semiconductors 功能描述:IC UART FIFO 5MBPS 3.6V 16TSSOP |
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