參數(shù)資料
型號: SC16IS740IPW
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù): 8/62頁
文件大?。?/td> 308K
代理商: SC16IS740IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
8 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
See
Section 7.4 “Hardware reset, Power-On Reset (POR) and software reset”
[2]
Selectable with IOControl register bit 1.
CS/A0
2
9
6
I
SPI chip select or I
2
C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt-trigger, active LOW). If I
2
C-bus configuration
is selected by I2C/SPI pin, this pin along with A1 pin allows user
to change the device’s base address.
SPI data input pin or I
2
C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data
input pin. If I
2
C-bus configuration is selected by I2C/SPI pin, this
pin along with A0 pin allows user to change the device’s base
address. To select the device address, please refer to
Table 32
.
SPI data output pin. If SPI configuration is selected by I2C/SPI
pin, this is a 3-stateable output pin. If I
2
C-bus configuration is
selected by I2C/SPI pin, this pin function is undefined and must
be left as n.c. (not connected).
I
2
C-bus or SPI input clock.
I
2
C-bus data input/output, open-drain if I
2
C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this
pin is an undefined pin and must be connected to V
SS
.
Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register
(IER). Interrupt conditions include: change of state of the input
pins, receiver errors, available receiver buffer data, available
transmit buffer space, or when a modem status flag is detected.
An external resistor (1 k
for 3.3 V, 1.5 k
for 2.5 V) must be
connected between this pin and V
DD
.
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin
programmable I/O pin or modem’s DSR pin
[2]
programmable I/O pin or modem’s DTR pin
[2]
programmable I/O pin or modem’s CD pin
[2]
programmable I/O pin or modem’s RI pin
[2]
UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send.
Writing a logic 1 in the modem control register MCR[1] will set
this pin to a logic 0, indicating data is available. After a reset this
pin is set to a logic 1. This pin only affects the transmit and
receive operations when auto RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware flow control
operation.
ground
The center pad on the back side of the HVQFN24 package is
metallic and should be connected to ground on the
printed-circuit board.
SI/A1
3
10
7
I
SO
4
11
8
O
SCL/SCLK
SDA
5
6
12
13
9
10
I
I/O
IRQ
7
14
11
O
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4/DSR -
GPIO5/DTR -
GPIO6/CD
GPIO7/RI
RTS
-
-
-
-
15
16
17
18
20
21
22
23
24
12
13
14
15
17
18
19
20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
-
-
10
V
SS
V
SS
9
-
19
-
16
[3]
center
pad
[3]
-
-
Table 2.
Symbol
Pin description
…continued
Pin
TSSOP16
Type Description
TSSOP24
HVQFN24
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