參數(shù)資料
型號: SC16C850IET,115
廠商: NXP Semiconductors
文件頁數(shù): 8/55頁
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 36-TFBGA
標(biāo)準(zhǔn)包裝: 1,000
特點: 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 36-TFBGA
供應(yīng)商設(shè)備封裝: 36-TFBGA(3.5x3.5)
包裝: 帶卷 (TR)
其它名稱: 935284685115
SC16C850IET-G
SC16C850IET-G-ND
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
16 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
6.10 Loopback mode
The internal loopback capability allows on-board diagnostics. In the Loopback mode, the
normal modem interface pins are disconnected and reconfigured for loopback internally
(see Figure 9). MCR[3:0] register bits are used for controlling loopback diagnostic testing.
In the Loopback mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
input pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and MCR[2]
(OP1). Loopback test data is entered into the transmit holding register via the user data
bus interface, D[7:0]. The transmit UART serializes the data and passes the serial data to
the receive UART via the internal loopback connection. The receive UART converts the
serial data back into parallel data that is then made available at the user data interface
D[7:0]. The user optionally compares the received data to the initial transmitted data for
verifying error-free operation of the UART TX/RX circuits.
In this mode, the interrupt pin is 3-stated, therefore, the software must use the polling
method (see Section 7.2.2) to send and receive data.
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
Table 7.
Baud rate generator programming table using a 1.8432 MHz clock when
MCR[7] = 0 and CLKPRES[3:0] = 0 …continued
Output
baud rate
(bit/s)
Output
16
× clock divisor
(decimal)
Output
16
× clock divisor
(hexadecimal)
DLM
program value
(hexadecimal)
DLL
program value
(hexadecimal)
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