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參數(shù)資料
| 型號： | SC16C850IET,115 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 18/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SINGLE W/FIFO 36-TFBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 特點(diǎn)： | 可編程 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.5 V ~ 3.3 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 36-TFBGA（3.5x3.5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935284685115 SC16C850IET-G SC16C850IET-G-ND |
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SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
25 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
7.3.1 FIFO mode
[1]
[2]
[1]
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see Section 6.4 “FIFO operation”).
Table 10.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7:6]
Receive trigger level in 32-byte FIFO mode[1].
These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16C850 will issue a receive ready interrupt when the number of
characters in the receive FIFO reaches the selected trigger level. Refer to
5:4
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode[2].
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
3
FCR[3]
reserved
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Table 11.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes) in 32-byte FIFO mode[1]
00
8
01
16
10
24
11
28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C850IET-G | 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C850IET-S | 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C850L | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface |
| SC16C850LIB,128 | 制造商:NXP Semiconductors 功能描述: |
| SC16C850LIB,151 | 制造商:NXP Semiconductors 功能描述: |
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