參數(shù)資料
型號(hào)： SC16C850IET,115
廠商： NXP Semiconductors
文件頁數(shù)： 20/55頁
文件大?。?/td> 0K
描述： IC UART SINGLE W/FIFO 36-TFBGA
標(biāo)準(zhǔn)包裝： 1,000
特點(diǎn)： 可編程
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5 V ~ 3.3 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應(yīng)商設(shè)備封裝： 36-TFBGA（3.5x3.5）
包裝： 帶卷 (TR)
其它名稱： 935284685115
SC16C850IET-G
SC16C850IET-G-ND
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
27 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Table 14.
Interrupt Status Register bits description …continued
Bit
Symbol
Description
Table 15.
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3
LCR[5:3]
Programs the parity conditions (see Table 16).
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see Table 17).
logic 0 or cleared = default condition
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 18).
logic 0 or cleared = default condition
Table 16.
LCR[5:3] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
XX
0
no parity
0
01odd parity
0
11even parity
1
0
1
forced parity ‘1’
1
forced parity ‘0’
Table 17.
LCR[2] stop bit length
LCR[2]
Word length (bits)
Stop bit length (bit times)
0
5, 6, 7, 8
1
15
11
2
16, 7, 8
2
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SC16C850IET-G 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850IET-S 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C850L 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
SC16C850LIB,128 制造商:NXP Semiconductors 功能描述:
SC16C850LIB,151 制造商:NXP Semiconductors 功能描述:
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