- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11830 > SC16C850IET,115 (NXP Semiconductors)IC UART SINGLE W/FIFO 36-TFBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | SC16C850IET,115 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 4/55頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SINGLE W/FIFO 36-TFBGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 特點(diǎn)： | 可編程 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.5 V ~ 3.3 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 36-TFBGA（3.5x3.5） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935284685115 SC16C850IET-G SC16C850IET-G-ND |
第1頁(yè)第2頁(yè)第3頁(yè)當(dāng)前第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
12 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C850 monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C850 will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data
may be sent.
When AFCR1[2] is set to logic 1 then the function of CTS pin is mapped to the DSR pin,
and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as
described above for CTS and RTS.
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be
forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.
However, the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16C850 will continue to accept data until the receive FIFO is
full.
When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature
register set’ are all zeroes, the hardware and software flow control trigger levels are set by
FCR[7:4]; see Table 6.
When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contain any value other than 0x00, the hardware and software flow control
trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines
how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is
sent. The content in FLWCNTL determines how many bytes are in the receive FIFO
before RTS (or DTR) is asserted, or Xon is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met, spurious operation of the device might occur. When using
FLWCNTH and FLWCNTL, these registers must be initialized to proper values before
hardware or software flow control is enabled via the EFR register.
6.6 Software flow control
When software flow control is enabled, the SC16C850 compares one or two sequentially
received data characters with the programmed Xon or Xoff character value(s). If the
received character(s) match the programmed Xoff values, the SC16C850 will halt
transmission (TX) as soon as the current character(s) has completed transmission. When
a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the interrupt output pin (if
receive interrupt is enabled) will be activated. Following a suspension due to a match of
the Xoff characters’ values, the SC16C850 will monitor the receive data stream for a
match to the Xon1/Xon2 character value(s). If a match is found, the SC16C850 will
resume operation and clear the flags (ISR[4]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27508E12B22SC | CONN RCPT 22POS BOX MNT W/SCKT |
| MS27484P12B35S | CONN PLUG 22POS STRAIGHT W/SCKT |
| MS27474P12B98P | CONN RCPT 10POS JAM NUT W/PINS |
| D38999/24WD15PN | CONN RCPT 15POS JAM NUT W/PINS |
| MS3116F-14-19S | CONN PLUG 19POS W/SOCKET SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C850IET-G | 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C850IET-S | 功能描述:UART 接口集成電路 16C 2.5-5V 5MBPS UART 128BFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C850L | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V single UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface |
| SC16C850LIB,128 | 制造商:NXP Semiconductors 功能描述: |
| SC16C850LIB,151 | 制造商:NXP Semiconductors 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。