參數(shù)資料
型號(hào): SC16C850IBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
封裝: SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<
文件頁(yè)數(shù): 38/55頁(yè)
文件大小: 394K
代理商: SC16C850IBS
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
38 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
8. Limiting values
Table 35.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
V
DD
supply voltage
V
n
voltage on any other pin
T
amb
ambient temperature
T
stg
storage temperature
P
tot
/pack
total power dissipation per
package
9. Static characteristics
[1]
Hysteresis input.
[2]
Except XTAL2; XTAL2 V
OL
is 1 V typical.
Sleep current might be higher if there is any activity on the UART data bus during Sleep mode.
[3]
[4]
Activated by LOWPWR pin.
Limiting values
Conditions
Min
-
V
SS
0.3
40
65
-
Max
7
V
DD
+ 0.3
+85
+150
500
Unit
V
V
°
C
°
C
mW
operating in free air
Table 36.
T
amb
=
40
°
C to +85
°
C; tolerance of V
DD
±
10 %; unless otherwise specified.
Symbol
Parameter
Static characteristics
Conditions
V
DD
= 2.5 V
Min
0.3
1.8
0.3
V
DD
= 3.3 V
Min
0.3
2.4
0.3
Unit
Max
0.45
V
DD
0.65
Max
0.6
V
DD
0.8
V
IL(clk)
V
IH(clk)
V
IL
clock LOW-level input voltage
clock HIGH-level input voltage
LOW-level input voltage
XTAL1 pin
XTAL1 pin
except XTAL1 clock,
LOWPWR pin
LOWPWR pin
except XTAL1 clock,
LOWPWR pin
LOWPWR pin
I
OL
= 4 mA
I
OL
= 2 mA
I
OH
=
4 mA
I
OH
=
800
μ
A
V
V
V
[1]
0.3
1.6
0.65
-
0.3
2.0
0.8
-
V
V
V
IH
HIGH-level input voltage
[1]
1.6
-
-
-
1.85
-
-
-
-
-
-
-
-
V
DD
-
0.4
-
-
10
10
30
30
3
50
50
5
2.2
-
-
2.2
-
-
-
-
-
-
-
-
-
V
DD
0.4
-
-
-
10
10
30
30
3
50
50
5
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
mA
μ
A
μ
A
pF
V
OL
LOW-level output voltage
[2]
[2]
V
OH
HIGH-level output voltage
[2]
[2]
I
LIL
I
LIH
I
L(clk)
LOW-level input leakage current
HIGH-level input leakage current
clock leakage current
LOW-level
HIGH-level
f = 5 MHz
I
DD
I
DD(sleep)
I
DD(lp)
C
i
supply current
sleep mode supply current
low-power mode supply current
input capacitance
[3]
[4]
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