參數(shù)資料
型號: SC16C850IBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
封裝: SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<1<Always Pb-free,;SC16C850IBS<SOT617-1 (HVQFN32)|<<http://www.nxp.com/packages/SOT617-1.html<
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代理商: SC16C850IBS
SC16C850
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Product data sheet
Rev. 2 — 11 November 2010
27 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15.
Bit
7
Table 16.
LCR[5]
X
0
0
1
1
Table 17.
LCR[2]
0
1
1
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
Table 14.
Bit
Interrupt Status Register bits description
…continued
Symbol
Description
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
LCR[6]
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
LCR[5:3]
Programs the parity conditions (see
Table 16
).
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Table 17
).
logic 0 or cleared = default condition
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 18
).
logic 0 or cleared = default condition
6
5:3
2
1:0
LCR[5:3] parity selection
LCR[4]
LCR[3]
X
0
0
1
1
1
0
1
1
1
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
LCR[2] stop bit length
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
Stop bit length (bit times)
1
1
1
2
2
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SC16C850IET 2.5 V to 3.3 V UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
SC16C850LIB 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
SC16C850LIBS 1.8 V single UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode parallel bus interface
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SC16C850IBS/Q900,528 制造商:NXP Semiconductors 功能描述:Cut Tape 制造商:NXP Semiconductors 功能描述:0