參數(shù)資料
型號(hào)： SC16C550BIN40,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 20/48頁(yè)
文件大?。?/td> 0K
描述： IC UART 40-DIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 可編程
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 935274386112
SC16C550BIN40
SC16C550BIN40-ND
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
27 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C550B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
[1]
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
Table 21.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
Data Carrier Detect. DCD (active HIGH, logical 1). Normally this bit is the
complement of the DCD input. In the loopback mode this bit is equivalent to
the OUT2 bit in the MCR register.
6
MSR[6]
Ring Indicator. RI (active HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loopback mode this bit is equivalent to the
OUT1 bit in the MCR register.
5
MSR[5]
Data Set Ready. DSR (active HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loopback mode this bit is equivalent to the
DTR bit in the MCR register.
4
MSR[4]
Clear To Send. CTS. CTS functions as hardware ow control signal input if it
is enabled via MCR[5]. The transmit holding register ow control is
enabled/disabled by MSR[4]. Flow control (when enabled) allows starting and
stopping the transmissions based on the external modem CTS signal. A logic
1 at the CTS pin will stop SC16C550B transmissions as soon as current
character has nished transmission. Normally MSR[4] is the complement of
the CTS input. However, in the loopback mode, this bit is equivalent to the
RTS bit in the MCR register.
3
MSR[3]
logic 0 = no DCD change (normal default condition)
logic 1 = the DCD input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
2
MSR[2]
RI[1]
logic 0 = no RI change (normal default condition).
logic 1 = the RI input to the SC16C550B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
1
MSR[1]
DSR[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
CTS[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
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