參數(shù)資料
型號(hào): SC16C550BIN40,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/48頁(yè)
文件大?。?/td> 0K
描述: IC UART 40-DIP
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-DIP
包裝: 管件
其它名稱: 935274386112
SC16C550BIN40
SC16C550BIN40-ND
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
18 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.
Register descriptions
Table 9 details the assigned bit functions for the twelve SC16C550B internal registers.
The assigned bit functions are more fully dened in Section 7.1 through Section 7.10.
[1]
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2]
These registers are accessible only when LCR[7] is set to a logic 0.
[3]
These functions are not supported in the HVQFN32 package, and should not be written.
[4]
OUT2 pin is not supported in the HVQFN32 package.
[5]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Table 9.
SC16C550B internal registers
A2
A1
A0
Register
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General Register Set[2]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
IER
00
modem
status
interrupt
receive
line status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
FCR
00
RX
trigger
(MSB)
RX
trigger
(LSB)
reserved reserved
DMA
mode
select[3]
TX FIFO
reset
RX FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
0
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
LCR
00
divisor
latch
enable
set break set parity even
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
MCR
00
reserved
auto ow
control
enable
loopback
OUT2[4]
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
transmit
empty
transmit
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
0
MSR
X0
DCD
RI
DSR
CTS
DCD
RI
DSR
CTS
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special Register Set[5]
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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