參數(shù)資料
型號(hào)： SC16C550BIN40,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 18/48頁(yè)
文件大小： 0K
描述： IC UART 40-DIP
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 可編程
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 935274386112
SC16C550BIN40
SC16C550BIN40-ND
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
25 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 19.
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
reserved; set to ‘0’
6
MCR[6]
reserved; set to ‘0’
5
MCR[5]
Auto ow control enable.
4
MCR[4]
Loopback. Enable the local loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and
RI are disconnected from the SC16C550B I/O pins. Internally the modem
data and control pins are connected into a loopback data conguration
(see Figure 11). In this mode, the receiver and transmitter interrupts
remain fully operational. The Modem Control Interrupts are also
operational, but the interrupts’ sources are switched to the lower four bits
of the Modem Control. Interrupts continue to be controlled by the IER
register.
logic 0 = disable loopback mode (normal default condition)
logic 1 = enable local loopback mode (diagnostics)
3
MCR[3]
OUT2. Used to control the modem DCD signal in the loopback mode.
logic 0 = OUT2 is at logic 1. In the loopback mode, sets OUT2 (DCD)
internally to a logic 1.
logic 1 = OUT2 is at logic 0. In the loopback mode, sets OUT2 (DCD)
internally to a logic 0.
2
MCR[2]
OUT1. This bit is used in the Loopback mode only. In the loopback mode,
this bit is used to write the state of the modem RI interface signal via
OUT1.
1
MCR[1]
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0]
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
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